Differential signal input to PMOD

[Yusuf7]

Hi,

I would like to know what IO standard would I use if I want to input a differential signal to two adjacent PMOD headers on PMOD JB. This differential signal will be an input to a buffer on the FPGA. The current xdc file on github uses LVCMOS33 as a default standard as shown below.

set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]

Would it be fine if I use LVCMOS33 or should I use another IO standard and if so which one should I use. I am using the Arty A7 100t board.

 

Thank you

[zygot]

2 hours ago, Yusuf7 said:

I would like to know what IO standard would I use if I want to input a differential signal to two adjacent PMOD headers on PMOD JB.

You don't mention what board you are using, but really it doesn't matter.

Just because a header has 2 pins next to each other doesn't mean that they are suitable as differential inputs. For inputs what really matters is what logic standard is driving your differential signal. But even if this is from a 3.3V differential source that doesn't mean that you can use any particular connector pins to receive the signal. Trace length mismatches between the + and - can easily create big problems. In theory you can add termination allowing FPGA pins on 3.3V powered IO Banks to receive 2.5V differential signals but since the termination will be some distance from the actual FPGA balls and not likely to have good signal integrity properties I'd advise against it.

Your best bet would be to create a small board that plugs into your PMOD and converts the differential signal into a LVCMOS33 compatible single-ended signal;  assuming that you have the know-how to do it. I assume that if you did you wouldn't have submitted the question.

Depending on the data rates it might be possible to just use the + or - signal; again assuming that you properly condition it to be 3.3V logic compatible.