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RISC-V on Nexys


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I tried the new Instant SoC from FPGA Cores on my Nexys 4 DDR (Nexys A7) board. Instant SoC is a C++ compiler that compiles C++ directly to a RISC-V processor and peripherals. The result is one vhdl file that I synthesized with Vivado. The only file I needed to add was the constraints file to map the signals to pins.
The code implements a simple inclinometer. This is a description of what the code does:

  1. Sleeps 100 ms
  2. Read accelerations from the on board accelerometer using SPI
  3. Calculates angles using floating point math (atan, sqrt)
  4. Removes the zero offset that is reset using the center button.
  5. Print angles with one decimal point on UART
  6. Set the angles on 7 segment display
  7. Calculates an effect on the 16-leds. A led is “rolling” to the direction the board is leaning.
  8. Repeat

A lot of the code was taken from Instant SoC class lib doc.

The "hardware section", first in the main file defines the IO etc. In this case I created the following objects:

...
int main(void)
{
//% hw_begin
    FC_IO_Clk Clk(100);        
    FC_IO_Out LED(16);
    FC_IO_SPI accel(1000000,0,8);
    FC_IO_UART_TX uart_tx(115200,32);
    FC_IO_SegmentDisplay s7(8,8,0);
    FC_IO_In button_center;
    FC_System_Timer timer;    
//% hw_end

    uart_tx << "\r\nInclinometer demo using Nexys\r\n"; 
  ...

When compiling this it resulted in a VHDL file with the following port signals:

...
entity nexys is
    port(
        Clk : in std_logic;
        LED : out std_logic_vector(15 downto 0);
        accel_SCLK : out std_logic;
        accel_MOSI : out std_logic;
        accel_MISO : in std_logic;
        accel_SSn : out std_logic;
        uart_tx : out std_logic;
        s7_seg : out std_logic_vector(7 downto 0);
        s7_sel : out std_logic_vector(7 downto 0);
        button_center : in std_logic
    );
end entity;

architecture IMPL of nexys is
...

And if you prefer Verilog there is also a Verilog header file generated:

...
module nexys(
    input  Clk,
    output [15:0] LED,
    output accel_SCLK,
    output accel_MOSI,
    input  accel_MISO,
    output accel_SSn,
    output uart_tx,
    output [7:0] s7_seg,
    output [7:0] s7_sel,
    input  button_center
);
endmodule
...

The system is free to download.

I have attached the bit file (zipped) so it is possible to see what the C++ does.

nexys.cpp nexys.xdc nexys_bit.zip

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