RobG Posted December 21, 2014 Share Posted December 21, 2014 Are there any plans to add more interpreters? Can users create their own? Link to comment Share on other sites More sharing options...
attila Posted December 22, 2014 Share Posted December 22, 2014 Currently custom interpreters and colored command/data stages are not supported. For MOSI and MISO separate SPI interpreters have to be defined. The skip of leading bits is intended to be able to cut the command bits, like in a simple communication with AD/DA converter, and to display only the actual data bits. Similar the unused ending bits can be trimmed. To display only the leading command can be done by trimming the rest of the bits. I will discuss with my team the suggested features. Thank you for your observation. Link to comment Share on other sites More sharing options...
RobG Posted December 21, 2014 Author Share Posted December 21, 2014 Could you add another signal to SPI interpreter? It would be nice to have both data lines (MISO and MOSI) in the single interpreter instead of two. Also, how about one more for things like R/S or D/C. I know I can add it as a separate signal, but if it was part of the group, it could control things like the color of interpreted data (so for example data bytes could be green and control bytes yellow.) Is that possible at all? Finally, it would be great to have a row for skipped bit when 9bit SPI is used (this bit is sometimes used for D/C) and and the ability for that bit to control the color (as above.) Link to comment Share on other sites More sharing options...
logansam Posted December 23, 2014 Share Posted December 23, 2014 Attila, we may want to start a thread in the suggestions section of the forum for things like this. Link to comment Share on other sites More sharing options...
RobG Posted December 26, 2014 Author Share Posted December 26, 2014 One more thing regarding UART interpreter. In my setup, 0x00 is interpreted as BREAK most of the time. When I set the baud rate to ~1% less than it is, everything works fine. Is the bit test performed at the beginning or in the middle of the bit? Link to comment Share on other sites More sharing options...
attila Posted December 26, 2014 Share Posted December 26, 2014 The bit test is performed in the middle of bit time window. In the next software version the bit windows will be marked. Thank you for the 1% observation. We might need to increase the tolerance before considering a zero transmission as break. At what UART rate and logic analyzer sample rate do you see this problem? Instead -1%, you might try using parity mark. In the next version you will be able to specify stop length too. Link to comment Share on other sites More sharing options...
RobG Posted December 29, 2014 Author Share Posted December 29, 2014 The bit rate was 250k (DMX.) Link to comment Share on other sites More sharing options...
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RobG
Are there any plans to add more interpreters?
Can users create their own?
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