Vivado - problems with simulation - beginner

[dabigado]

I am a senior electrical engineering student and I just had my first interview at a local technology company and they offered me a second interview! However, they gave me a problem to solve of which i am pretty far into to it, at least far enough to start simulating some components.

 

I am new to vivado and FPGA's in general and I have spent about 5 hours today trying to figure this error out. My code shows zero warnings or errors and I verified that the file in question is indeed in the directory that it is looking for.

 

Wondering if anyone else has run into anything similar?

 

Log Stuff:

 

Tcl Console output when trying to simulate:

 

launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Entry_MachineTB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Entry_MachineTB_vhdl.prj"
The system cannot find the file specified.
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
ERROR: [USF-XSim-62] 'compile' step failed with error(s) while executing 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim/compile.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

Batch File:

 

'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim/compile.bat' script is:

@echo off
REM ****************************************************************************
REM Vivado (TM) v2018.3 (64-bit)
REM
REM Filename : compile.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Sat Jan 19 23:30:54 -0800 2019
REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
REM
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
REM usage: compile.bat
REM
REM ****************************************************************************
echo "xvhdl --incr --relax -prj Entry_MachineTB_vhdl.prj"
call xvhdl --incr --relax -prj Entry_MachineTB_vhdl.prj -log xvhdl.log
call type xvhdl.log > compile.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
:END
exit 1
:SUCCESS
exit 0

 

I have verified that the "Entry_MachineTB_vhdl.prj" file is indeed in the same directory as the batch file.

 

if needed, i can provide the code that i am working on.

 

Thanks for any help provided!! :D

[jpeyron]

Hi @dabigado,

I would look at the Vivado Design Suite Tutorial Logic Simulation and the Vivado Design Suite User Guide Logic Simulation.  I would also look at some tutorials like here and here. Remember to give you signals an initial value when simulating.

thank you,

Jon