I am new to FPGA. I have a Basys 3 board and am working on one of the tutorials 'getting started with the vivado IP integrator'. I got 'INFO: [Common 17-206] Exiting Vivado at Thu Nov 8 20:16:49 2018...' when I tried to generate bitstream. Could anyone help me out? I would really appreciate it!
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Min
Hi everyone,
I am new to FPGA. I have a Basys 3 board and am working on one of the tutorials 'getting started with the vivado IP integrator'. I got 'INFO: [Common 17-206] Exiting Vivado at Thu Nov 8 20:16:49 2018...' when I tried to generate bitstream. Could anyone help me out? I would really appreciate it!
Thanks!
Min
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