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problem with Vivado 2018.1 bitstream generation


Min

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Hi everyone,

I am new to FPGA. I have a Basys 3 board and am working on one of the tutorials 'getting started with the vivado IP integrator'. I got 'INFO: [Common 17-206] Exiting Vivado at Thu Nov  8 20:16:49 2018...' when I tried to generate bitstream. Could anyone help me out? I would really appreciate it!

Thanks!

Min

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Hi @Min,

Welcome to the forums. I moved your post to a better section for the topic. Here is a xilinx AR that has the "INFO: [Common 17-206] Exiting Vivado".  Please attach a screen shot of your block design.  Here is the Basys 3 resource center.  Have you gone through the Installing Vivado and Digilent Board Files tutorial?  Are you able to run the abacus demo

thank you,

Jon

 

 

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Hi @jpeyron,

Thanks very much for your help! I attached a screen shot of my block design. I did Installing Vivado and Digilent Board Files tutorial twice. I had no problem of running the abacus demo. Do you think I need to pay for the 'core licence agreement'? 

Thanks again,

Min

BlockDesign.png

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Hi @Min,

Generally you don't pay for license agreements, you just have to agree with them and I don't think we have any material with the Basys 3 that would require to purchase anything from Xilinx. What version of Vivado are you using and can you attach a picture of the error you are getting?

Thanks,
JColvin

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