Timing constraints are not met.

[greedyhao]

Hello,

When I following The Zynq Book Tutorials（exercises 5b） , I met a error unfortunately. It says that 'Timing constraints are not met.'.

I have no idea how to solve it. Could anybody do me a favor.

timing_1.rpx

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More detail shows below:

[n3wbie]

Hi,

I also did tutorials but didn't occur this problem. However, you can set false path or create clock group to fix your timing error.

 

Reference: https://www.beyond-circuits.com/wordpress/tutorial/tutorial16/

[jpeyron]

Hi @greedyhao,

Could you attach a screen shot of your block design, the warnings/errors in the vivado messages? Which tutorial are you attempting?

thank you,

Jon

 

 

 

[jamey.hicks]

To solve a timing problem, you need to dig into the timing report. From your screenshot, we can see there are failing intra-clock timing constraints on clk_fpga_0. In order to resolve the failures, you need to look at what paths are failing.

You posted the .rpx file but it's easier to look at the report outside Vivado.

[greedyhao]

Hi @jpeyron

Thanks in advance. I'm sorry to reply so late because the time in China is time to sleep.

Here is my block design:

 

[greedyhao]

Hi @n3wbie,

Thank you for your reply. I had looked through the link you offered.

But I still don't know set which two clock into a group. Please forgive my poor knowledge of the fpga.

Regards,

[n3wbie]

Hi @greedyhao,

Go to Implementation -> Edit Timing Constraints -> Set Clock Groups

 

Then another window will open and you just have to put the names of clock there:

Hope this helps.

[greedyhao]

Hi @n3wbie,

Thank you for you help. But setting clock group seems like not working.

[n3wbie]

Hi @greedyhao,

After you have done that, have you re-run the implementation?

 

 

[greedyhao]

Hi @n3wbie

Of course.

[greedyhao]

Hi @jamey.hicks

I had edited my question to post a screen of failing path. The error point to an IP called lms . But the IP core is provided by Zynq book.

[xc6lx45]

is it possible that this block isn't meant to be used at 100 MHz?

There are 27 levels of logic, the signal needs 18 ns through the transistors alone plus another 15 ns for routing delay. The design demands the signal to be ready after 10 ns...

I may be wrong, observing from the distance, but this looks like a typical beginner mistake in the "IP block" (if this is 3rd party, non-Xilinx): Leave sufficient registers = delay in any non-critical path. Done consistently, it will also speed up P&R tremendously - the  job gets so much easier.
If it were an output from the IP block, you could fix the situation by running the output through a chain of ~ 5 registers, and turning register rebalancing on in the options.

But, I suspect, this was tested with a lower-frequency clock (e.g. 12 MHz from USB is popular)

 

 

[tt12345678]

I have just come across the same problem as @greedyhao and was wondering if anyone else has. The tutorial involves using IP generated from the Matlab HDL coder in a previous tutorial, but they also provide the packaged IP for those, like me, who don't have access to Matlab. I'm using Vivado/Vitis 2020.1 and the tutorial uses software from 2015 so it took a bit of effort to get things to work at, e.g. port names were different from those in the provided constraints file and the IP Makefiles didn't work, but everything built in the end.

In fact, the whole thing runs on the Zedboard but the noise cancellation (the LMS filter) doesn't work. The system is supposed to take audio input, add tonal noise, perform noise cancellation and output the resulting audio. You can switch the output between original input, input + noise and the filtered signal but the filtered signal is the same as the noisy signal. The timing problems seem to be something to do with updating the adaptive filter's weights and I guess the filter has no effect because the weights never get updated but I don't really know.

It may not be possible to fix it easily as the IP was provided with the tutorial but it would be nice to understand what's gone wrong. However, as a complete beginner I don't have a clue where to start so I'd be grateful for any advice.

Thanks

[tt12345678]

Many apologies: in fact, the system works perfectly, I just didn't read the instructions properly (you have to press a button to operate the LMS noise canceller). I'm still puzzled as to what the timing warnings mean.

[JColvin]

Hi @tt12345678,

Unfortunately, I'm not really able to comment too much on the timing warning related to the LMS IP in the Zynq Book beyond what was previously said by others in this thread.

Thanks,
JColvin