Zybo Z7 DMA Audio Demo - not working

[melisa]

Hi,

I am trying to implement Audio Demo on Zybo Z7 using this: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-dma-audio-demo/start

First, I wanted to do it just using Vivado 2018.2 (without SDK). I followed what is described in this comment:

Bitstream is succesfully generated with two following warnings:

[Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).

 

I tried to fix this warnings using Xilinx and Diligent forum, but wasnt successful. Device is programmed but the audio demo is not working (when I press BTN1 and after BTN2 I can not hear anything on headphones).

Any suggestions/solutions are very well welcomed.

Regards,

[ArKay99]

According to the response by jpeyron:

Quote

The Vivado version unfortunately does make a difference. This project was originally made in an older version and updated to Vivado 2016.4 just recently. I just got this project working in Vivado 2017.1 by first going into the folder and editing the version to 2017.1 in the design_1_bd.tcl  found here \Zybo-DMA-master\src\bd\design_1\hw_handoff. Once you have loaded the project upgrade the ip cores by going to tools tools->report->report status and upgrade all ip cores. Next you need to have vivado create a wrapper and then generate a bitstream. In SDK i only imported the dma and not the dma_bsp. then i created a new board support package calling it dma_bsp. I verified the terminal portion of the project worked.

I haven't done this project, but went through upgrading the Out Of The Box  demo from my Zybo Z7 020 board from 2016.4 to 2018.2, which has a playback version of the DMA for audio. I have completed that and have it working and learned a lot. But I installed and worked with the 2016.4 version of the tools so I could build and run the project, then peruse the code. I am about to get into this project myself, so I'm interested in your results.

Did you do what was suggested?

1: The version IS important. if you are using a new version of the tools (2018.2 vs 2016.4) you have to tell the tcl what version you are running, I believe it's because the IP's are versioned. So, I would make the edit as outlined, then load the project, upgrade the ip cores. Then I would do the next steps, create wrapper and generate the bitstream.

2: There is a software component that has to be tied to the hardware component and that has to be done through the SDK. I believe the software component has to be upgraded through a new hw_handoff component (generated by exporting hardware with bitstream), then importing the correct projects in the SDK, and then creating a new board support package which will create a new fsbl project (IIRC).

Then you can program the Zync, once you've set up the SDK project properly.

Lastly, if you don't want to go through all of that, I didn't for the demo project as it was too much for a newb just starting out with the tools, I went to Xilinx and downloaded Vivado 2016.4 and checked the SDK, so I didn't have to do a separate dl for that too. You can have multiple versions of the tools on the machine at once. This way you won't have to go through the extra layer of determining what is different between the two versions and determine the cause and subsequent resolution just to get to a working project.

[melisa]

Hi,

Thanks for your answer.

1. I did everything that is outlined in number 1 section, and I have done every step that @jpeyron mentioned above in Vivado 2018.2.
2. I don't have that much experience with SDK, so I was wondering is it possible to launch this demo on my Zybo board only with Vivado project or it has to be launched to SDK?
 

P.S. @jpeyron has sent me step to upgrade this project in SDK, but I didn't try it yet because of my question 2.

Thanks a lot in advance.

 

[ArKay99]

As I said, I haven't done this project yet and it's possible that the SDK isn't used as the Zynq can be programmed and run with just the PL. However, when I looked at the project description I saw this...

Quote

Since this is a Vivado SDK Project, you can either directly launch SDK and import the hardware handoff, or you can generate a bitstream in Vivado before launching SDK. Select the hardware handoff options in the tutorial if you don't want to modify the project block design later.

This says to me that the hardware has already been built in Vivado and the next step is to work with the SDK, by either importing the hardware handoff or generate the bitstream in Vivado, export the hardware, and include the bitstream in the export, which will create the hardware handoff, then launch the SDK from the menu in Vivado.

So, if you've already done the Vivado update part as outlined by jpeyron, then I would incorporate what he's suggested to update the SDK portion of the project.

I'm still new to the Xilinx tools, but I would do it the latter way, genetate a bitstream in Vivado before launching the SDK, export the hardware (including the bitstream), then launching the SDK from within Vivado. Once I get the project up and running that's when I go back and start changing, adding or subtracting things and see what my changes do while learning the system. The SDK is sensitive to changes in the hardware and will add or subtract and recompile what it needs to keep the software up to date with the hardware.

[melisa]

Hi @ArKay99,

I finally did it :). Only thing after launching SDK is to create your own dma application with dma_bsp and import demo files as File System (not existing project as written there).

But I don't hear anything on headphones. I tried with line input and mic input. SDK terminal is giving messages (start recording, start playback etc.) but I hear nothing.

 

I would appreciate if anyone has advice for this problem.

Regards,

 

[jpeyron]

Hi @melisa,

Please add a screen shot of your sdk, block design as well as what you get in the serial terminal. Are you getting any errors? It might be easier to use vivado 2016.4 which is the version this demo was made in.

thank you,

Jon

[melisa]

Hi everyone,

Just to let you know that Demo version is upgraded to Vivado 2018.2 on Digilent github

 

Thanks everyone for help and patience.

Regards,

Melisa

[AndyCap]

Hi Guys,

 

There is an issue with the python script in the git repository:

	config.read("%s\config.ini" % script_dir)

 

This doesn't work on Linux, the slash is wrong.

 

Cheers

 

Andy

 

[AndyCap]

The example code also doesn't work.

It is using the LineOut, not much good as the Zybo hasn't got this. Needs changing to use the headphone out.

The function of button 1 and button 3 are also swapped.

[jpeyron]

Hi @AndyCap,

I have not had a chance to verify these issues but I did reach out to our content team about your findings.

thank you,

Jon