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Found 5 results

  1. Hi Everyone! I need help using the following pmodi2s2 module: - https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ I want to use it to sample audio data from microphone only. So, I've added the i2s receiver IP into my block diagram (attached) and run block automation. Following is the documentation of the IP core I used: - https://www.xilinx.com/support/documentation/ip_documentation/i2s/v1_0/pg308-i2s.pdf The following is a reference manual for the above mentioned PMOD module: - https://reference.digilentinc.com/pmod/pmodi2s2/reference-manual I also created an extra clock in PL fabric named FCLK_CLK1 (11.289MHz requested and got 11.290323 MHz). I couldn't find a PMOD core for the said module so I guessed I'll "make-external" and "constraint" the pins on to the PMOD header in a .xdc file. Now, I don't know what to connect where except for the lrclk_out, sclk_out and sdata_0_in which are obvious from their names. Rest of the configuration is auto generated by block automation. I'm particularly confused regarding the clocking and reset configuration. Please help me out on this I'll highly appreciate.
  2. I am new to this so I am just guessing how to out stuff together. I want to use the PmodI2S2 for Stereo Audio Input and Output. I am using a Cora z7 with a ZYNQ. I want to try and make two things: A. Connect the PmodI2S2 via Axi and then write a software application in Vitis to send and receive audio data. B. Connect the Pmod12S2 to logic and modify audio data. Possibly make an oscillator. The "Pmod I2S2 FPGA Volume Control Demo" in the resources centre says it uses an AXI streaming interface. So for part A. I made a new IP with an AXI streaming interface (just one way for line out) and a Pmod output that wraps some of the example code (removing the loop back bit). Then I connected it to DMA. and the DMA to the zynq. Not sure if this makes sense to do.. design_2.pdf But then I am not sure how I get the address in vitis. do I just use the dma address ? I can't work out how it is all translated/mapped. Or.... should I be using a FIFO/ buffer in hardware and writing larger amount of data at a time ?? Is AXI streaming correct should I use something else ? When I create new IP I have the choice: Lite/Full/Stream but when I edit the IP in the packager and add interfaces the AXI interfaces have the following: What is what in here ?? For Part B The example loopback code uses the AXI streaming interface, but what should I use in logic or what would be a normal design for moving audio samples around in fpga ?? Any help
  3. tara901

    USB audio on PYNQ-Z1

    Hi there, I am pretty new to using the pynq-z1 board. I wish to do some audio recording via a usb microphone! I am struggling with doing this successfully, is anyone able to help me with this? I am getting "no soundcards found" when issuing alsa commands arecord -l and aplay -l. I understand pynq -z1 receives audio samples as PWM or PDM, but im not sure exactly what that means in terms of linux drivers available. any help would be appreciated! Thanks
  4. I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  5. Hi, I am trying to establish a lowpass filter to Audio Demo code of Nexys A7 board. I have implemented a filter however i hear just a noise. If you share your time, i will be happy. I have added the project which was generated by Vivado 2018.2. Vivado Project Best regards.