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Arty-Z7-20: Some tutorials ported to Vivado 2017.4


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I recently ported two tutorials for Vivado 2017.4 - the actual Arty-Z7 examples are not fully ported to that version. They are available on github:



The XADC demo is originally written in Verilog - because I am usually using VHDL I took this as an occasion to dig deeper into that example. Also, I added a simulation bench (which normally is the first step when creating custom logic)

The second project is a port from Xilinx UG1165 tutorial using the centralized DMA IP. This was a bit tricky due to differnt RAM size and a strange error in Vivados connection automation (see that post: Wrong connection on AXI, evtl. somebody might provide ans answer?). I recommend working through UG1165, you'll learn a lot about how to use the SDK even sometimes you'll need to guess how to adapt to the Arty. There areĀ  also covered a lot of things concerning IPs and IP Integrator, so I feel, the additional time spent there is worthwhile.

Please note that repositories might contain issues, I did not test to the full extend. If theres someting missing, please feel free to add or correct or leave me a message.

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