hamster Posted January 24, 2016 Posted January 24, 2016 I got a bit bored yesterday, and hooked the PMODmic3 up to my PMODamp3 design, and put a small delay (of 32768 samples). The VHDL module for the microphone interface is actually surprisingly small : ---------------------------------------------------------------------------------- -- Engineer: Mike Field <hamster@snap.net.nz> -- -- Module Name: pmod_mic3 - Behavioral -- -- Description: Sample input form a PMOD_MIC3, once every 256 ticks of the -- master clock (mclk). ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity pmod_mic3 is Port ( mclk : in STD_LOGIC; sclk : out STD_LOGIC; cs : out STD_LOGIC; sdat : in STD_LOGIC; de : out STD_LOGIC; sample : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0')); end pmod_mic3; architecture Behavioral of pmod_mic3 is signal counter : unsigned(7 downto 0) := (others => '0'); signal data_sr : std_logic_vector(11 downto 0) := (others => '0'); begin process(mclk) begin if rising_edge(mclk) then de <= '0'; if counter > 5 and counter < 6 + 16*8 then cs <= '0'; else cs <= '1'; end if; if counter(2 downto 0) = 0 then data_sr <= data_sr(10 downto 0) & sdat; end if; if counter = 17 * 8 then --------------------------------------------- -- convert the 12-bit unsigned sample to the -- lowest 12 bits of a 16-bit signed sample -- by adding it to -2048 --------------------------------------------- de <= '1'; sample <= std_logic_vector(to_unsigned(63488,16) + unsigned(data_sr)); end if; sclk <= std_logic(counter(2)); counter <= counter + 1; end if; end process; end Behavioral; If interested, the rest of the code is at http://hamsterworks.co.nz/mediawiki/index.php/MIC_and_AMP
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