Arty PLL implementation?

[ASICs]

Hi everyone,

I'm sure that someone has used a PLL in an Arty design....I have tried and keep getting an implementation error as follows:

[DRC 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity. The signal xilinx_ip_pll/inst/clk_in1 on the xilinx_ip_pll/inst/plle2_adv_inst/CLKIN1 pin of xilinx_ip_pll/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.

The Arty Clock100 comes in on Pin E3, so I'm assuming that this is a clock capable input..? (can't be moved...) I even tried instantiating a BUFH in the top level before the PLL input and no dice...

New to Vivado so I'm sure that this is another basic cockpit error...

Thanks in advance.

Paul

 

[JColvin]

Hi Paul,

I personally don't know if we have any nice PLL implementation examples running around, but I've asked some of our applications engineers if they have happened to work with them for the Arty board. They'll get back to you here on the forum.

Thanks,
JColvin

[cristian.ignat]

Hello Paul,

Can you give us the sources? Also please tell me which version of Vivado are you using.

Regards,

Cristian

[hamster]

At the moment I never use IP blocks, and have had no trouble with the PLL primitives... here's a couple of suggestions.

1) Are you sure you have the correct package selected? I know it sounds dumb, but it happens!

It should be xc7a35ticsg324-1L, but on older versions of Vivado that package isn't there. Using the Automotive -2L part seems to work.... (any suggestions from others???? 

2) Try a BUFG.