nexys 4 ddr UART

[bri]

What is max baud rate of UART on Nexsys4 DDR board?  Datasheet for  FT2232H indicates slower speeds when using RS232.  I looked on schematics for Nexsys4 DDR and don't see part so couldn't check how it is actually wired up.  Also trying to understand end-end application to FPGA connections in terms of flow control.  Trying to bring data into board through RS485 PMOD that I can't flow control so thought I might be able to use FPGA to manage flow control and output data out of UART to host PC and store to file.  Trying to understand max data rates, how much buffering I need in FPGA, etc.  Not sure if processor running software on FPGA would be better or just implement in hardware.

[jpeyron]

Hi @bri,

We do not have a metric for max baud rate through the usb uart. Here is a forum thread that discusses higher baud rates with the usb uart that should be useful. Here is an article the might be useful as well.

thank you,

Jon

[bri]

Are you saying you don't know the max bandwidth that can be achieved (throughput) or you don't know what is the maximum the interface can be configured to (physical bus speed)?

[JColvin]

Hi @bri,

I apologize for the delay. It is more along of the lines of we don't know the maximum throughput that can be achieved with the Nexys 4 DDR. In theory, the chip can support speeds up to 12 MBaud though.

Thank you,
JColvin

[zygot]

15 hours ago, JColvin said:

In theory, the chip can support speeds up to 12 MBaud

This depends on what you are trying to do. As I understand it what you want to do is get data from your FPGA board into a PC. On the PC side I doubt that you'll find anything close to 12 Mbaud as a supported COM port data rate. ( I don't use Win10 and for Win7 device manager 128000 is the highest baud rate that you can set a COM  port to). But how are you going to read your data? Windows makes serial port applications very difficult. Python is nice and works for both Windows and Linux but I doubt that interpreted Python code will support anything close to that rate. Perhaps compiled Python executables might... Maximum data date also depends on how much data you want to transfer at a time. Understand that your OS is task switching and may not be interested in running your application long enough to support really large continuous data transfers even though the rate is slow compared to the processor clock. I have used interpreted Python applications and 921600 without flow control to transfer 500K+ bytes to an FPGA board though a USB COM port and WIn7. 

As to whether you need a processor operating the UART in your FPGA the answer is definitely NO. You can control the UART better and easier in logic. There are UART logic implementations available in your favourite HDL.

If you decide that flow control is a good idea ( hint hint.... ) then you can buy a cheap TTL USB UART cable or breakout board using the same or similar FTDI part and have flow control. This is my preferred way to connect an FPGA to a PC ( if I'm using a UART ).  I have also connected FPGA boards to SBCs like the Minnowboard and UP^2 board at higher data rates using MRAA.

I would make the pitch that trying to calculate maximum data rates is not as straight forward as you might want to think it is, especially if you don't have a lot of experience experimenting in how to achieve it... and an understanding of software ( especially OS layers of software ) behaviour. What might work most of the time for short data transfers might be less reliable for large, uninterrupted, streams of data. The FPGA end should be the simplest part and certainly the most straightforward to analyse

I didn't get the part of your question about RS-485. I can say that once you abandon the realm of digital logic and go to RS-232 or RS-485 levels you cannot expect data rates much above 1 Mbaud as the voltage swings are considerably larger than 3.3V logic.