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Hi @Mostafa Ayesh I might be misunderstanding your question, but you can modify your script to use loops. Several example scripts in the application show this, see below for an example. Thanks. Arthur

Hi @mwnoble1910, The maximum input frequency spec for the ADP5250's digital channels is 100 MHz, even when sampling at 1 GS/s. The specifications can be found here: https://digilent.com/reference/test-and-measurement/analog-discovery-pro-5250/specifications Thanks, Arthur

Hi @LHji There are no significant differences between the Zmod DAC 1411 and the Zmod AWG 1411. The DAC was renamed to the AWG. Projects that say they can use one can use either. No Eclypse demo projects created by Digilent have releases for 2022 versions of the tools yet. If you need to use this version of the tools, you should download examples targeting an earlier version of the tools and open the projects in the newer version. This may require installing an the earlier tool version that a particular project targets to recreate an XPR project file. There may also be changes to IP that break compatibility between versions. Thanks, Arthur

Hi Donald, Here are a couple of posts with some more information on how you might approach further debugging this issue: If your host system is a Windows computer: If you're on Linux, please check this thread instead: Thanks, Arthur

Hi stevers, Yes, the names of the checkout and checkin scripts were shortened. Functionality should not be affected. Thanks, Arthur

The ports you are referring to are likely interface ports, which are effectively buses made up of multiple individual ports/signals. Check your HDL wrapper file to determine the actual ports which are created for your design - I expect you will find sixteen inouts instead of two output ports, see below for an example with one interface port. Thanks, Arthur

It depends on your XDC file. Pin 1 of the IP/module is intended to be connected to Pin 1 of the physical pmod port (same goes for the rest of the pins, 2-4, 7-10). However, the XDC file decides what pin on the IP actually connects to what physical FPGA pin. This means you can constrain one module's pins 1-4 to pins 1-4 of JA, constrain another module's pins 1-4 to pins 7-10 of JA, and pins 7-10 of both modules to whatever other FPGA I/O is available.

I would assume it's fine to use other unconnected pins, but I'm not sure. The AD1 IP doesn't connect any signals to the pins, it just needs to know that they are there. I'd mostly be concerned about something like shorting an output logic high to ground, but that shouldn't happen here with no actual output signal, and no path to ground from the pin.

Assigning random pins should work. I'd suggest using pins from another Pmod port, if you have any that are unused/free.

Yes, as long as you are using make external, you need to use two AD1 modules to control two Pmod AD1s, and you are able to constrain the each module's ports to the pins of a single Pmod port. The Pmod pins you use for each port in this case are arbitrary - you can map whatever module port to whatever physical location using the XDC - so top row and bottom row is doable. Thanks, Arthur

Hey Udayan, No, a single Pmod AD1 controller only controls a single Pmod AD1. Assuming you use the board file interface, it must be connected to the top row of the Pmod port the module is attached to - due to limitations of the Pmod IP when its used in this way, the lower four pins must be constrained, but are not attached to any logic in the FPGA. Thanks, Arthur

Hi Steve, welcome to the forums. The Pmod NAV was designed to be used with the SPI interface - it's classified as a SPI Pmod - and Digilent hasn't tested it with I2C and doesn't have any material on using it this way. That said, looking through the NAV schematics and datasheets for the parts, it seems like it might be possible, there are pullup resistors and slave addresses don't seem to conflict. You'd still need to pull CS high to enable I2C. Good luck, Arthur

Hi @jay2718 The Nexys A7 uses an Artix FPGA which is very different from a Zynq part, since the latter has a hard processor. Materials created for Zynq devices would not get you over the initial hump. Zynq devices tend to be better suited to running Linux than FPGA-only parts, since the latter need to use up a bunch of FPGA resources to implement a soft-core processor and memory controller. Partly because of this, Digilent doesn't provide any guides for getting Linux running on the Nexys. Thanks, Arthur

Hi @Cezara Welcome to the forums. As the Pmod ISNS20 is retired, we won't be able to provide much in the way of support on it, however, in broad strokes: The ISNS20 communicates using SPI. This means that in order to talk to it, a host board needs to implement a SPI controller. There are different ways to go depending on what you are trying to do: You might go out and find a SPI controller someone has already written and instantiate it in your design. You might roll your own controller. If you were using Microblaze, you might use a Xilinx built-in AXI QSPI controller. In any of these cases, you need to check the datasheets for the parts on the Pmod to ensure that the controller you use meets the timing and SPI mode requirements. Depending on what you're trying to measure, you might also be able to use the JXADC port without the Pmod, by measuring across a resistor or some other similar setup. Thanks, Arthur

Hi @3STTW N17 and N18 are PL I/O pins - the I2C interface for the codec is connected to the PL I/O banks rather than the PS. You can connect a PS I2C peripheral to these pins via E(xtended)MIO, however Digilent doesn't have any examples which do this. In order to determine which MIO (or EMIO) pins a peripheral is connected to, you add the Zynq PS block to a block diagram, apply the preset configuration to it using block automation, and open up it's configuration wizard. This is also where you are able to change which I/Os a peripheral is connected to. In the case of using EMIO, you will also need to make sure the EMIO pins are connected to ports in the block design, and add location constraints to place those ports on the right physical I/O pins. Here's a screenshot of where to find out which peripherals are enabled and connected to which MIO pins: And a screenshot of how to create ports which connect to the new I2C EMIO port on the Zynq PS block: Thanks, Arthur

Hi Bob, welcome to the forum!

Hi @Yongjun As you've mentioned, the Digital Discovery's pattern generator buffer is only 32k, and can't be increased past this. You could do multiple patterns in a row: fill up the patterns buffer with one set of data, push it out, then replace it with another set of data, push that out, and so on; to get to the necessary total buffer length, using WaveForms SDK or the Scripts instrument in the application. That said, you wouldn't be able to get a full sample rate in either situation, since there's still PC-side software involved for both. The DigitalOut_Custom example could be a good starting point for this. There's also a pattern generator example in this guide: https://digilent.com/reference/test-and-measurement/guides/waveforms-sdk-getting-started Thanks, Arthur

Hi @nikk Based on the name of the IP in the block design, I would expect the Quad SPI's device ID xparameters macro to be XPAR_AXI_QUAD_SPI_0_DEVICE_ID, but I could be wrong. Where are you pulling XPAR_SPI_0_DEVICE_ID from? Have you tried stepping through the XSpi_Transfer function in the debugger to see where exactly it is getting stuck? Thanks, Arthur

Hi @gongou Detailed instructions on how to modify an HDL-only project to boot from SPI flash can be found here: https://digilent.com/reference/learn/programmable-logic/tutorials/arty-programming-guide/start The guide is somewhat out of date and was created for the original Arty board before it was renamed to the Arty A7 (-35T and -100T), but everything is still be largely the same. If you want to boot a Microblaze design, different steps are required, please let us know if that's what you are trying to do. Thanks, Arthur

Hi @robb XADCdemo.v also needs to be modified in order to access other XADC channels. The lines setting the value of the Address_in register ("Address_in <= 8'h1C;") and using the channel_out signal ("channel_out == 8'h1C") hardcode XADC DRP register addresses that correspond to the XADC results registers. The demo as posted only reads from channels 12 (address 0x1C) and 0 (address 0x10). See Xilinx UG480 for more info on the register space of the DRP interface. Thanks, Arthur

Hi @Eran Zeavi If you haven't already, you should install the board files for the Zybo Z7: Instructions are here. The board files include a Zynq preset which is applied to the PS IP during Block Automation, which includes all of the relevant DDR configuration settings. Which examples are you trying to use? In general for PL-to-DDR configuration, you will need some kind of DMA controller. The DMA Audio and HDMI demos for the Zybo Z7 implement several different Xilinx DMA IP, and include Zynq PS configurations. Thanks, Arthur

Hey @davidgrimm I apologize for the delayed response. In order to boot on power-up (instead of just when PROG is pressed), the "Master SPI x4" configuration mode needs to be selected in synthesis settings. Section 2 of the (fairly old, but still usable) Basys 3 Programming Guide covers how to do this, along with setting a higher than default clock rate and enabling bitstream compression, to improve the configuration speed. Alternatively, you can add the following three lines to your XDC file. I've also since added these same lines to the master XDC file for the Basys 3 on Github. Thanks! Arthur

If bit-banging a seven segment "protocol" through GPIO isn't working well, you might consider writing a custom seven segment controller, adding it to a block design through "Add Module", and connecting it to an AXI GPIO to provide a simple interface from the processor. The custom logic might only need to include a counter that drives the C pin and a mux to select 7 from a set of 14 bits that the processor can write to. Using this stub verilog module: It can be wired to an AXI GPIO and external ports like this: Thanks, Arthur

To keep the topic contained in one place, I'm going to address this question over here: Thanks! Arthur

Sounds like the ZC706 board files might not have Pmod interfaces defined. In this situation, you can create external ports and write constraints for the Pmod pins manually. Check out the second half of the "Adding GPIO Peripherals to a Block Design" section of this guide on Reference: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#add_gpio_peripherals_to_a_block_design. Since the Pmod GPIO IP uses a different interface from the AXI GPIO, the top-level port names that need to be written into the XDC file may differ. You can check for the names you need to constrain by opening the HDL wrapper file after you've validated your block design and created the wrapper. - You should see some pins like "Pmod_out_0_pin1_io". See below for an example: Note that you can also use the same method with an AXI GPIO IP. Thanks, Arthur