LHji

I used a beta version Waveforms 3.19.11 with my EclypseZ7 board having zmod ADC and DAC installed. It works okay. Today I download the newer Waveforms V3.20.1 but failed to connect to the board. It saids, Device update required, with error; Device EclypseZ7 rev:201.cfg:0 WF:3.20.1 FDWdevice OpenEx The reason I switched to newer version Waveforms is because it allows me to use deeper ADC and DAC buffers. Looking for you help and Thanks, LH Ji

Where can I find the definitions of Xs, Rs, Xp, and Rp used in impedance measuring? For a parallelly connected RC circuit the measured Xs is a negative number and Xp is positive number.

We had a Analog Discovery 2 board. We have the following questions about this 5V "tolerant": 1. Can we use "Open drain" with a pull up resistor to translate the digital output to 0 or 5V? 2. Can we use "open drain" for IO pin that is configured as clock or pulse? 3. What is the recommend pull up resistance value? Thanks

I ahve two questions about the impedance analyzer in Waveforms. 1. The meaning of Rs, Xs, Rp Xp vakue? I assume Rs and Xs are the impedences of R and C(or) L connected in serial, and Rp and Xp are the impedances of R and C(or) L connected in parallel. 2. How can I change the reference resistor ro a large one than 1 Mohm? My DUT has a capacitor ~200pF and parallel resistor ~10G ohm. I think we need a ~10 Gohm reference resistor for accurate impedance measuring in 0.01Hz to 1 Hz range. Thanks

Hi Attila, Thanks. It solved my problem.

Hi Udayan, I tried but stopped after saw many timing violations in implementation of Vivado.

Can anyone there show me a working CS project that talks a real board, particularly Eclypse Z7 board? I can run the Py samples without problem. But I had problems when running C++ sample, have both compiling and runtime errors.

Hi Attila, Thanks for your code. Will try it later this week.

I need to implement a digital output as pulse train, which has the following parameters: 1. External digital trigger; 2. Programmble delay; 3. Programmable duty cycle; 4. Programmable polarity. I am a c/c++ coder, could you please show me an example code? Thanks

I still have problem to connect Eclypse board to Waveforms. I can't program QSPI. SO I used SD boot by copy the "DCFG_07_01_01.bin" to SD card. The Waveforms version I used is 3.19.11 64bit Qt5.15.2 (Waveforms beta) There are there problems: 1. This version can't detect my board (connected through USB). 2. My device is not listed -->Device Fix, There are two device listed: 1. 00000000 "" SN: and 2. 00000172 "digilent USB Device B" SN210393 3. However there is no "Eclypse Z7" listed in product pull-down list.

Hi zygot, Thanks for your advice. I will try Waveforms and see how it works for me.

zygot, Thanks for your info. Do you know where I can download the "old 125MHz" ADC and DAC ZMODs codes from? The online support documents are so difficult for a beginner like me. Do you know the other way I can talk to the tech support person in Digilent? Thanks

We purchased a Zmod DAC1411 board and tested it with Eclypse Z7 board with baremetal demo project. The maximum sample update rate we can have is ~33Msample/second. This rate is lower than claimed 100Msample/second. The only parameter related to update frequency is "frequencyDivider" in ZmodDAC1411 library. The update rate stops change when this parameter is set to <2. It seems the HW IP used PS core clock (66MHz) for DAC output sample clock. Is this update rate limit caused by the provided hardware wrapper, "design_1_wrapper_hw_platform_0"? Can we change it to use higher DAC clock? Thanks,

Thanks, How about the Ip core and library? Can I use these Ip cores and library in 2022 version Vivado/Vitis?

We purchased Eclypse Z7 with ZMOD scope and ADC1411 boards recently, which is planned to be used to generate 2 analog signal and a few digital signals as stimulis to our test circuit. The 2 ADC inputs will be used to monitor the test circuit outputs. By checking the examples provided by Digilent, we have the following questions: 1. The DAC board we purchased is labelled as Zmod DAC 1411. Can we use Zmod AWG ip core and it's responding library for this board? 2. The ADC board we have is Zmod Scope. Can we use Zmod ADC1410 ip core and it's responding library for this board? 3. The latest Xilinx tool version is Vivado/Vitis2022. Can I use this newer tool for examples for 2019.1 or 2019.2 version? 4. Is there any Zmod ADC and Zmod DAC example projects for Vitis 2022 version available? 5. What is the design flow you recommended for a Zynq 7 beginner who knows some embedded and FPGA (withhout PS)? Thanks