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JColvin

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Posts posted by JColvin

    Pmod wifi SDK problem

    in FPGA

    Posted

    Hi @jonpaolo02 and @rzsmi,

    I apologize for the long delay.

    I was able to get the Pmod WiFi up and running on Vivado and SDK 2019.1 (on Windows 10) successfully. I needed to download the latest Vivado Library from the Digilent GitHub (https://github.com/Digilent/vivado-library) since some changes were made to the compilation order on the Pmod WiFi a few months ago, and made sure that I had Vivado choose that repository via the Settings->IP->Repository within the Project Manager on the right-hand side of the Vivado GUI. I have attached a picture of my Block Design that I used.

    Otherwise, within SDK for completeness sake, I created a blank c++ application, deleted the main.c that came with it, and copied over the HTTPServer (since it already includes the same materials as the WiFiScan) from the hw_platform in the examples folder to the src folder within the application, made the appropriate WiFi SSID and password changes in the HTTPServerConfig.h file. I also made some changes in the deWebIOServerSrc.cpp file to make sure the appropriate input and output pins were added to the PinPage.htm via the addPINs function.

    I will test this on Vivado 2019.2 and Vitis/SDK 2019.2 as well.

    Please let me know if you have any questions about this.

    Thanks,
    JColvin

    Zedboard WiFi 2019-1 block design.PNG

    Cmod A7-35T Demo Project

    in Project Vault

    Posted

    Hi @skywalker,

    Which Digilent blog post were you looking at which linked to this forum thread? I know the Cmod A7 Resource Center in the Example Projects section links to this forum thread (after I got permission from zygot to do so), but I would like to make sure that our blog posts link to the correct information.

    Additionally, the reason you had to regenerate the bitstream for step 4 for the Cmod A7 OOB demo was because you were using Vivado 2018.3 when the release was designed for Vivado 2018.2.

    Thanks,
    JColvin

    JTAG HS3 compatible IDC ribbon cable....??

    in Other

    Posted

    Hi @Starglow,

    We do have a cable that will connect to the host board, https://store.digilentinc.com/jtag-2x7-ribbon-cable/, but it does not have the male header to connect to the JTAG HS3, and all of headers that Digilent sells have a 2.54 mm pitch rather than the 2.00 mm pitch that Xilinx choose for their JTAG integration. I did do a Digikey search (though you are welcome to browse your favorite source for these) for a list of compatible headers that should work in your situation; the only thing I was not able to specify in the search was the 0.5 mm square posts to ensure the pins remain secure in the plastic header.

    Let me know if you have any questions about this.

    Thanks,
    JColvin

    JTAG-HS2 program issue

    in FPGA

    Posted

    Hi @Chase,

    Have you tried closing out ISE iMPACT and then re-opening it and/or restarting the computer? Occasionally drivers can get confused about what is connected; I've run into this same issue before and successfully resolved it in that way. As an additional question, have you successfully gotten the downstream Spartan-6 device to be detected before? Do you have Digilent's Adept software open at the same time as iMPACT?

    If that doesn't work, we can troubleshoot further.

    Thanks,
    JColvin

    Unable to retrieve video from a PCAM example on a Zybo z7-10

    in FPGA

    Posted

    Hi @makedestroyrepeat,

    Do you know what resolutions you selected? Based on the Pcam 5C demo, it appears that only the 1080P at 30Hz and the 720p at 60Hz are supported and selecting 1080p at 15Hz will cause problems if used. What size/resolution is your monitor that you have connected? Did you also choose the RAW mode as the Image Format?

    Additionally, what version of Vivado and Xilinx SDK are you using so I can see if I can replicate this?

    Thanks,
    JColvin

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