Viktor Nikolov

One note to add, Zynq PS settings also differ, which can cause trouble when porting a project between boards. There are some options for how to do the port, but the easiest is usually to rebuild the block design from scratch in a new project. Alternatively, it may be possible to export a Zynq preset after doing block automation in a new project, and apply that preset to the project targeting the original board.

It was all about Data Cache invalidation calls!
In the main.c attached, I demonstrate the successful transfer of 16,777,215 32bit words (==64 MB) as a single packet, which is the largest possible DMA transfer by the AXI DMA IP (because the max. width of Buffer Length Register is 26bit).
This main.c is intended for the Vitis 2023.1 workspace @artvvb shared in the previous post.
First, I fixed in the code the bug Arthur mentioned on 24 April 2024: Data Cache invalidation calls have to be made with length RECV_BUFFER_SIZE * sizeof(u32).
After this fix, I saw the same behavior as Arthur. The last 5 values in the received buffer were zeroes.
Edit: This happens for DMA transfers of all lengths (I tested it down to 1,000) when RECV_BUFFER_SIZE==words_per_packet. The Xil_DCacheFlushRange() and Xil_DCacheInvalidateRange() apparently "forget" to work on the last 5 words of the memory range.
Then I added an additional 16 bytes to the data length passed to the Data Cache functions in the function ReceiveData():
Xil_DCacheFlushRange( buf_addr,      RECV_BUFFER_SIZE * sizeof(u32) + 16 ); ... Xil_DCacheInvalidateRange( buf_addr, RECV_BUFFER_SIZE * sizeof(u32) + 16 ); That did the trick. With the cache invalidated with an extra 16 bytes, the DMA transfer works as documented.
Edit: This seems to be an undocumented feature of Xil_DCacheFlushRange() and Xil_DCacheInvalidateRange(). When I read comments in the source code xil_cache.c, I get impression that the problem is caused by end of the buffer not being aligned with cache line. This forum post from @asmi confirms it.
 
main.c

You can use the output of XADC Wizard IP in the PL when you enable the "Enable AXI4Stream" option.
Recently, I created HW design following this tutorial: Signal Processing with XADC and PYNQ - Hackster.io
(I used only the HW design from that tutorial.)
The XADC Wizard IP can output measurement data as an AXI Stream, which is a pretty simple protocol. In the HW design I mention here, the AXI stream is fed into the AXI-Stream Subset Converter IP (to divide the stream into chunks of 128 records by setting the tlast signal) and then into AXI DMA IP to load it into memory accessible by Zynq ARM core.
Nevertheless, you can process the AXI Stream coming from the XADC Wizard IP using any PL logic you want.
I have attached the PS code I used in my experiment. It doesn't communicate with the XADC Wizard IP in any way. It only calls routines working with the AXI DMA IP.
The "magic" of getting data into AXI DMA IP happens solely on the PL level.
 
main.c

The Arty A7 board file comes with the configuration for MIG.
For instructions on setting up the MIG on Arty A7, you can refer to the first chapter of this tutorial. The tutorial is focused on MicroBlaze; nevertheless, setting up the MIG is the same for both MicroBlaze and PL logic.

Hi!
In a project of mine, I want to use this 3.5″ 480x320 TFT SPI display based on the ILI9488 display controller. 
I, therefore, ported the ILI9488 Arduino library for use on AMD Xilinx SoC and FPGA. The integral part was porting of the Adafruit_GFX library because the ILI9488 library is based on it. I removed all Arduino-specific code, optimized SPI writes for the capabilities of Xilinx SPI libraries, and made other modifications.
I published the library and sample projects on the GitHub repository.
You can see the capabilities of the library in this video.
I tested the library on AMD Xilinx Zynq-7000 SoC and Artix-7 FPGA (running on MicroBlaze soft CPU).
The repository contains sample projects that run on Digilent boards Zybo Z7, Arty A7 and Cmod A7.
I also provided a detailed step-by-step tutorial on how to use the display on the Zynq board Cora Z7.
The library supports both Zynq Processing System SPI and AXI Quad SPI IP.
The library also supports both Zynq Processing System EMIO GPIO and AXI GPIO IP.
Different kinds of SPI and GPIO can be combined (e.g., you can use AXI SPI with PS GPIO and vice versa). All four combinations are supported by the library. Three out of four combinations are showcased by the sample projects in the repository.
I tested the ILI9488 library with a standalone application running on ARM core or MicroBlaze. I believe it should also work on a PetaLinux app.
Viktor

Hi Viktor!
I just wanted to write a quick message to thank you for your detailed help. After some trial and error, and finding an oscilloscope to borrow, I managed to get everything working. You're right, I'd like to use my board for something more complex, but this was a great introduction for a beginner. Thanks again!
Kim