How to read Cora Z7-07S analog inputs from Custom IP

[DavideDevoti]

Hi,

in my Vivado project for Cora Z7-07S I added a custom IP connected with AXI-Lite I/F to PS and so far I've been able to connect digital I/O to the IP after having defined the ports in vhdl code of the IP as in/out std_logic and then connecting them to ports created at the main level following the names reported in the costraint file.

In the picture above there is a screenshot of a part of my design. davide_hdlc_0 is my custom IP block, ck_io10 amd ck_io11 are Cora Z7 IOs and I've connected them to two IP inputs.

My question is now : how I can do the same for analog inputs, for example if I want to read single ended analog data from A0 ? I think I will have to uncomment the following lines in the xdc file

set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]

but after having done this how I can connect this input to my custom IP ? That is what kind of input port I have to create in my custom IP and how I can connect this port to the physical analog input source ?

Thanks

Davide

[Viktor Nikolov]

My understanding is that you need to use the XADC Wizard IP to access the ADC of the Zynq.

Digilent provides Cora Z7 XADC Demo project. I used it recently, and it worked pretty well. I opened the 2021.1 version available for download in Vivado 2023.1 and was able to upgrade it and generate outputs without issues.

[DavideDevoti]

Hi Viktor,

thanks for the reply. By the way I think that with XADC Wizard IP you can only read analog input values in your PS application while I would like to process them directly in the PL.

[Viktor Nikolov]

8 hours ago, DavideDevoti said:

I think that with XADC Wizard IP you can only read analog input values in your PS application while I would like to process them directly in the PL.

You can use the output of XADC Wizard IP in the PL when you enable the "Enable AXI4Stream" option.

Recently, I created HW design following this tutorial: Signal Processing with XADC and PYNQ - Hackster.io
(I used only the HW design from that tutorial.)

The XADC Wizard IP can output measurement data as an AXI Stream, which is a pretty simple protocol. In the HW design I mention here, the AXI stream is fed into the AXI-Stream Subset Converter IP (to divide the stream into chunks of 128 records by setting the tlast signal) and then into AXI DMA IP to load it into memory accessible by Zynq ARM core.

Nevertheless, you can process the AXI Stream coming from the XADC Wizard IP using any PL logic you want.

I have attached the PS code I used in my experiment. It doesn't communicate with the XADC Wizard IP in any way. It only calls routines working with the AXI DMA IP.
The "magic" of getting data into AXI DMA IP happens solely on the PL level.

 

main.c

Edited April 22 by Viktor Nikolov
typo fixed

[artvvb]

For what it's worth, you can also use the Zynq XADC with the DRP interface - no AXI interfaces involved - though AXI stream is likely simpler. This is a demo for the Zybo that uses it without programming any software image into the PS: https://digilent.com/reference/programmable-logic/zybo-z7/demos/xadc.

Thanks,

Arthur

[artvvb]

36 minutes ago, Viktor Nikolov said:

 

The XADC Wizard IP can output measurement data as an AXI Stream, which is a pretty simple protocol. In the HW design I mention here, the AXI stream is fed into the AXI-Stream Subset Converter IP (to divide the stream into chunks of 128 records by setting the tlast signal) and then into AXI DMA IP to load it into memory accessible by Zynq ARM core.

Using the subset converter as a small packetizer is nice, I didn't realize it had that feature, great tip!