aleib_borgwarner

Hi @aleib_borgwarner
There are a bunch of ways to control the ports of a custom RTL module from Zynq PS. The topic in general is communication between Zynq PS and PL (FPGA fabric). What approach you pick heavily depends on the requirements of the interface you want to control. How often you need to provide new values every clock cycle and whether values need to be provided even when the processor is busy doing other things are both relevant.
A couple of options to look into, in roughly ascending order of complexity/difficulty:
1. AXI GPIO
2. "Hard" PS peripherals like GPIO connected to fabric through EMIO.
3. AXI stream FIFOs
4. A custom AXI controller
5. DMA
You could also connect ports to external hardware, potentially via the Pmod port.
As for permanent programming, the board can be booted from flash or an SD card - see this guide: https://digilent.com/reference/programmable-logic/guides/zynq-baremetal-boot
Thanks,
Arthur

For the C side of things, AXI peripherals all get mapped to specific memory addresses in Vivado. As long as you know the base addresses and register map, you can do reads/writes to an AXI controller's registers by just doing reads/writes to their memory addresses. This could be as simple as something "value = (*my_register_address);" for a read. In Xilinx drivers, this is usually abstracted away through a bunch of macros and an API, with some hardware-design-specific information (like base addresses) coming in through xparameters.h.

The sales blurb for the Eclypse-Z7 still says "The Eclypse Z7 is specifically designed to enable the rapid prototyping and development of embedded measurement systems.. reducing the time it takes for engineers and researchers to develop innovative and powerful new high-speed instrumentation, control, and measurement systems for edge-computing, medical, and communications applications."
Curious as to whether this describes your experience with the board and support so far. I haven't cloned the repositories in quite a while and an hour ago I find that just getting basic information, like how many contiguous ADC samples does the AXI controller support, has gotten a lot harder to find. Still looking by the way.
If your application mostly is implemented in your PL logic and you only need a simple, low speed way to write control registers and read status registers to control your design, the simplest way might be to use the spare PS UART, through the EMIO, to connect your software to your logic. The basic idea can be found in the tutorial: https://forum.digilent.com/topic/22512-manipulate-pl-logic-using-ps-registers/ It might not be appropriate for your requirements, but if it is the effort to get your design working might be a whole lot easier. It might be worth looking at.
 

The Eclypse-Z7 is not the ideal platform for this kind of project. Consider looking at something along the lines of the XEM7320. everything will be a lot easier and quicker once you get familiar with their closed framework. That said, you can certainly ignore all of the ZYNQ cores on the Eclypse-Z7 and do everything in the PL, without being tied to any vendor IP like AXI bus implementation ( which can be sketchy ). The old but venerable Z7020 PL is pretty much equivalent to an Artix 75T in terms of resources. Here is such a project that I did a while ago:
There's an XEM7320 version also posted.
If you are going to invest your time and effort into developing an application on an FPGA platform, why not choose one that allows you to use that effort to do more ambitious projects in the future?

Hey @artvvb

Thank you for the quick response and pointing me in the right direction! I will take a look at the "low-level filter demo" and start moving my efforts towards redesigning the HW; I didn't realize the limited access I had with a SW approach.

Will keep you posted if there's anything else I have questions about!

Thanks again!