Zybo-Z7-20 Uart Problem in RISC-V

[drkome]

I wrote my own RISCV processor. and I tested it on Zybo z7-20 board. I did not experience any problems in many tests. But I tried to do the Dhrystone test. I noticed something in the simulation when all print commands were working correctly while filling the fifo correctly. The FPGA was also causing problems while communicating with the console.

See part of the image above as an example. The first 2 prints fill the UART's fifo correctly in the simulation. And the uart is created successfully.

Vivado Simulation.

Uart application in console. And I didnt see  "ee_printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");" in this console. while it works fully and accurately in the simulation. Is there a problem with it working this way on FPGA? Is this definitely an implementation problem? I using  Zybo-z7-20.  I make this RTL with 20MHZ.  UART spec 115200 baudrate.