Why is the Pmod HYGRO only able to read from the top pins of the ZYBO Z720?

[ilovefpga]

I am coding C++ in Vitis 2019.2 on the Zybo Z720 and I am only able to get temperature readings from pin 1-6 of the Pmod port. Currently trying to get the Pmod HYGRO to be able to read from both top 6 pins and bottom 6 pins, how do I do that? Attached are the code used and readings which I got from the top 6 pins and bottom 6 pins respectively. 

This is my Vitis code

Readings from top 6 pins of the Pmod port (accurate reading)

Readings from bottom 6 pins of the Pmod port (error reading)

[thinkthinkthink]

HUGE DISCLAIMER! You'll have to write your own I2C driver using the iic functions in Xilinx's embeddedsw repo (XIic_MasterRecv, XIic_MasterSend etc.).

Add the two AXI IIC IPs to your block design and let Run Connection Automation do its job or you can manually make the IIC ports external. Then go to our XDC Repo and get the Zybo-Z7-Master constraints file. 

Right click on Constraints and select Add Sources. 

Click on Add Files and look for the .xdc file wherever you downloaded/saved it on your PC. Make sure Copy Constraints files into project is checked, this makes it so if you modify this .xdc file (which you will) you'll still have a fresh unmodified original which can then be imported into other projects.

Uncomment the lines corresponding to the Pmod port which you'll want to use, in this example I'm using JD but because of the HYGRO and AQS pmod pinout you'll only need to uncomment jd[2], jd[3] and jd[6], jd[7].

This is the pinout for the PmodAQS and you might want/need to also use the IO/INT or WAKE/RST pins so make sure to read through its Reference Manual.

Make the following changes in the XDC, Validate Design, Generate Bitstream and you're good to go.

 

[thinkthinkthink]

This is the pinout of the PmodHYGRO, to be able to use it on both top and bottom rows of a Pmod port you're going to need to use two AXI IIC IPs, or just one AXI IIC together with the I2C controller inside the ZYNQ processing system, with their interface IIC constrained to the Pmod port (one top row and the other bottom row) you're going to plug it into (double check to make sure you've nailed the pinout correctly). The PmodHYGRO IP also has an AXI TIMER inside it so maybe you're gonna want to add that to your block design as well (although you might be able to manage without it, not sure, since the ZYNQ also has some timers inside).

[ilovefpga]

Hi @thinkthinkthink sorry for the late reply, this is my current block diagram. Do you mind further explaining  about using the two AXI IIC IPs to be able to use both top and bottom rows of the Pmod port. Would I then be able to use Pmod HYGRO on the top Pmod port and Pmod AQS on the bottom Pmod port? (trying to free up one extra port for another AD1)

[ilovefpga]

Thanks for the response thinkthinkthink, I found another method yesterday which was fairly simple and gave it a quick test and ended up working.

Link to the similar procedures