Walking a 1 through a vector, which logic is better?

[FlyingBlindOnARocketCycle]

To control the 4 digit seven segment LED's on the Basys3 I need to mux the data by controlling the anode signal.  

I made a counter: (possibly a terrible resource hungry counter)

seg_mux_clk: process(clk_240)--cycle through the 4 sev seg displays
   begin
   if rising_edge(clk_240) then
        cnt <= (cnt + 1)mod 4;
  end if;
 end process;

next I have my one hot logic which I have recently decided to change. I have nothing to back this up but I suspect that the FPGA can more easily handle shifting a bit than it could handle multiplying a number.  Believing the shift requires less logic also makes me think its overall better for timing.  What you do you guys think?

old version:

an_i <= not std_logic_vector(to_unsigned(2 ** cnt,an_i'length));

New version:

an_i <= not std_logic_vector(shift_left(to_unsigned(1,an_i'length) ,cnt));

 

PS if you are wondering why I don't just have a process that uses cnt as an unsigned, set cnt to 1 and mulitply it by 2 each clock cycle (1,2,4,8,1,2,4,8,....) , its because my displayed data is an array. This keeps my data and the proper seven segment in sync.

seven_seg_out_reg: process(clk_240)
    begin
        if rising_edge (clk_240) then 
            seg <=  display(cnt);
            an  <= an_i;
        end if;
    end process; 

[hamster]

Hi, 

The common way would be to use slices of the std_logic_vector:

signal seg : std_logic_vector(3 downto 0) := "0001";

...

if rising_edge(clk_240) then
  seg <= seg(2 downto 0) & seg(3);
end if

or the opposite way:

if rising_edge(clk_240) then
  seg <= seg(0) & seg(3 downto 1);
end if

You most likely also want a concurrent statement to assign the value to the module's output, and allow for the fact that the display are usually active low (ii.e. digits are switched on when the output is 0).

    seg_output <= not seg;

This also helps, because if 'seg'_output is declared as being "out" in the module definition you can't read it's value to update it (yes, a little bit silly for VHDL).

VHDL does have ROL, ROR, SLA and SRL operators, but nobody uses them as far as I know.