Display Decimal Point in Basys 2

[vizia]

I was able to successfully a hexadecimal counter on one of the four seven segment displays (Select to display on one of them). I can't seem to understand how to display a decimal point. My code is attached below. I want to display a decimal point in front of or before one of the signed four-bit numbers to demonstrate a negative. 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity main_signed4bitnumbers is
		Port ( Seg : out STD_LOGIC_VECTOR (7 downto 0);
			Din : inout STD_LOGIC_VECTOR (3 downto 0);
			Sel : inout STD_LOGIC_VECTOR (1 downto 0);
			AN : inout STD_LOGIC_VECTOR (3 downto 0)
			);
end main_signed4bitnumbers;

architecture Behavioral of main_signed4bitnumbers is

begin

procselect: process(Sel)
	begin
		if (Sel = "00") then AN <= "0111";
		elsif (Sel <= "01") then AN <= "1011";
		elsif (Sel <= "10") then AN <= "1101";
		elsif (Sel <= "11") then AN <= "1110";
	end if;
end process procselect;


myproc1:process(Din)
	begin
		case Din is

			when "0000" => Seg <= "1000000"; -- '+0'
			when "0001" => Seg <= "1111001"; -- '+1'
			when "0010" => Seg <= "0100100"; -- '+2'
			when "0011" => Seg <= "0110000"; -- '+3'
			when "0100" => Seg <= "0011001"; -- '+4'
			when "0101" => Seg <= "0010010"; -- '+5'
			when "0110" => Seg <= "0000010"; -- '+6'
			when "0111" => Seg <= "1111000"; -- '+7'
			when "1000" => Seg <= "1000000"; -- '-0'
			when "1001" => Seg <= "1111001"; -- '-1'
			when "1010" => Seg <= "0100100"; -- '-2'
			when "1011" => Seg <= "0110000"; -- '-3'
			when "1100" => Seg <= "0011001"; -- '-4'
			when "1101" => Seg <= "0010010"; -- '-5'
			when "1110" => Seg <= "0000010"; -- '-6'
			when "1111" => Seg <= "1111000"; -- '-7'
			when others => Seg <= "1111111"; -- 'nothing'

		end case;
end process myproc1;


end Behavioral;

 

[jpeyron]

Hi @vizia,

Sorry i mis-spoke about it being VHDL.  If you look at the always case statement it has 8 bits. If you look at the assignment line and the always case statement the DP pin is always given 0. So with your vhdl code it would be something like the vhdl code attached below. Just make sure you ucf file includes the DP pin.

Spoiler

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity main_signed4bitnumbers is Port ( Seg : out STD_LOGIC_VECTOR (8 downto 0); Din : inout STD_LOGIC_VECTOR (3 downto 0); Sel : inout STD_LOGIC_VECTOR (1 downto 0); AN : inout STD_LOGIC_VECTOR (3 downto 0) ); end main_signed4bitnumbers; architecture Behavioral of main_signed4bitnumbers is begin procselect: process(Sel) begin if (Sel = "00") then AN <= "0111"; elsif (Sel <= "01") then AN <= "1011"; elsif (Sel <= "10") then AN <= "1101"; elsif (Sel <= "11") then AN <= "1110"; end if; end process procselect; myproc1:process(Din) begin case Din is when "0000" => Seg <= "10000000"; -- '+0' when "0001" => Seg <= "11110010"; -- '+1' when "0010" => Seg <= "01001000"; -- '+2' when "0011" => Seg <= "01100000"; -- '+3' when "0100" => Seg <= "00110010"; -- '+4' when "0101" => Seg <= "00100100"; -- '+5' when "0110" => Seg <= "00000100"; -- '+6' when "0111" => Seg <= "11110000"; -- '+7' when "1000" => Seg <= "10000000"; -- '-0' when "1001" => Seg <= "11110010"; -- '-1' when "1010" => Seg <= "01001000"; -- '-2' when "1011" => Seg <= "01100000"; -- '-3' when "1100" => Seg <= "00110010"; -- '-4' when "1101" => Seg <= "00100100"; -- '-5' when "1110" => Seg <= "00000100"; -- '-6' when "1111" => Seg <= "11110000"; -- '-7' when others => Seg <= "11111110"; -- 'nothing' end case; end process myproc1; end Behavioral;

thank you,

Jon

[jpeyron]

Hi @vizia,

Here is a 7 segment tutorial from FPGA4FUN with the DP included in VHDL.  

thank you,

Jon

[vizia]

8 minutes ago, jpeyron said:

Hi @vizia,

Here is a 7 segment tutorial from FPGA4FUN with the DP included in VHDL.  

thank you,

Jon

Finally an online implementation of DP - I couldn't find anything online myself. Only thing is that it is in Verilog but I'll try to understand how it works and update you. Thank you, Jon!

[vizia]

22 minutes ago, jpeyron said:

Hi @vizia,

Sorry i mis-spoke about it being VHDL.  If you look at the always case statement it has 8 bits. If you look at the assignment line and the always case statement the DP pin is always given 0. So with your vhdl code it would be something like the vhdl code attached below. Just make sure you ucf file includes the DP pin.

  Reveal hidden contents

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity main_signed4bitnumbers is Port ( Seg : out STD_LOGIC_VECTOR (8 downto 0); Din : inout STD_LOGIC_VECTOR (3 downto 0); Sel : inout STD_LOGIC_VECTOR (1 downto 0); AN : inout STD_LOGIC_VECTOR (3 downto 0) ); end main_signed4bitnumbers; architecture Behavioral of main_signed4bitnumbers is begin procselect: process(Sel) begin if (Sel = "00") then AN <= "0111"; elsif (Sel <= "01") then AN <= "1011"; elsif (Sel <= "10") then AN <= "1101"; elsif (Sel <= "11") then AN <= "1110"; end if; end process procselect; myproc1:process(Din) begin case Din is when "0000" => Seg <= "10000000"; -- '+0' when "0001" => Seg <= "11110010"; -- '+1' when "0010" => Seg <= "01001000"; -- '+2' when "0011" => Seg <= "01100000"; -- '+3' when "0100" => Seg <= "00110010"; -- '+4' when "0101" => Seg <= "00100100"; -- '+5' when "0110" => Seg <= "00000100"; -- '+6' when "0111" => Seg <= "11110000"; -- '+7' when "1000" => Seg <= "10000000"; -- '-0' when "1001" => Seg <= "11110010"; -- '-1' when "1010" => Seg <= "01001000"; -- '-2' when "1011" => Seg <= "01100000"; -- '-3' when "1100" => Seg <= "00110010"; -- '-4' when "1101" => Seg <= "00100100"; -- '-5' when "1110" => Seg <= "00000100"; -- '-6' when "1111" => Seg <= "11110000"; -- '-7' when others => Seg <= "11111110"; -- 'nothing' end case; end process myproc1; end Behavioral;

thank you,

Jon

That did work! Finally!!! Thanks so much Jon, I spent hours trying to find this!

[jpeyron]

Hi @vizia,

Glad to hear that worked for you.

cheers,

Jon