On page 19 is the timing diagram, where I have set up the DAC to operate as in Figure 2. (DCKI_Q = 0, DCK_TADJ = 000)
From the timing table on page 8, for t11 and t12, setup time t11 = 570, and hold time t12 is -170.
Because the hold time specified in the LTC2000A datasheet is negative, it looks like the data can be released before the clock edge?
I am using a Virtex 7 at 375MHz, xc7vx485tffg1761-2 (active)
The 375MHz clock comes from a high speed ADC, which goes to a MMCM to generate the FPGA system 375MHz clock, where clk_in1 of the clk_wiz_inst is the output of the selectio_wiz input IP that forwards the clock coming from the high speed ADC.
The 375MHz system clock clocks the selectio_wizard output IP for the DACs.
The CLK_375M_OBJ is the source clock for the forwarded clock.The create_clock and create_generated_clock statements are following the timing reports.
Spoiler
report_timing -hold -to [get_ports PVo_DAC1_DA_P]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins -max_paths 1 -nworst 1 -delay_type min -sort_by slack.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
| Date : Fri Feb 9 14:28:27 2018
| Host : SV2104 running 64-bit Service Pack 1 (build 7601)
| Command : report_timing -hold -to [get_ports PVo_DAC1_DA_P]
| Design : FSA_Main_wrapper
| Device : 7vx485t-ffg1761
| Speed File : -2 PRODUCTION 1.12 2014-09-11
------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -0.168ns (arrival time - required time)
Source: FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].oddr_inst/C
(rising edge-triggered cell ODDR clocked by CLK_375M_OBJ {rise@0.000ns fall@1.334ns period=2.667ns})
Destination: PVo_DAC1_DA_P[0]
(output port clocked by Po_DAC1_DATCLKIN_P_obj {rise@0.000ns fall@1.334ns period=2.667ns})
Path Group: Po_DAC1_DATCLKIN_P_obj
Path Type: Min at Fast Process Corner
Requirement: 0.000ns (Po_DAC1_DATCLKIN_P_obj rise@0.000ns - CLK_375M_OBJ rise@0.000ns)
Data Path Delay: 0.809ns (logic 0.809ns (100.000%) route 0.000ns (0.000%))
Logic Levels: 1 (OBUFDS=1)
Output Delay: 0.170ns
Clock Path Skew: 0.999ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.530ns
Source Clock Delay (SCD): 0.457ns
Clock Pessimism Removal (CPR): 0.074ns
Clock Uncertainty: 0.148ns ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.027ns
Discrete Jitter (DJ): 0.080ns
Phase Error (PE): 0.093ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock CLK_375M_OBJ rise edge)
0.000 0.000 r
BUFR_X1Y9 BUFR 0.000 0.000 r FSA_Main_i/selectio_LDV1/inst/clkout_buf_inst/O
net (fo=55, routed) 0.255 0.255 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_in1
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.447 -1.192 r FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.759 -0.433 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.407 r FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clkout1_buf/O
net (fo=3, routed) 0.035 -0.372 FSA_Main_i/util_ds_buf_0/U0/BUFGCE_I[0]
BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O)
0.026 -0.346 r FSA_Main_i/util_ds_buf_0/U0/USE_BUFGCE.GEN_BUFGCE[0].BUFGCE_U/O
net (fo=164918, routed) 0.803 0.457 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_in
OLOGIC_X0Y8 ODDR r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].oddr_inst/C
------------------------------------------------------------------- -------------------
OLOGIC_X0Y8 ODDR (Prop_oddr_C_Q) 0.192 0.649 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].oddr_inst/Q
net (fo=1, routed) 0.000 0.649 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/data_out_to_pins_int[0]
AN30 OBUFDS (Prop_obufds_I_O) 0.617 1.266 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].obufds_inst/O
net (fo=0) 0.000 1.266 PVo_DAC1_DA_P[0]
AN30 r PVo_DAC1_DA_P[0] (OUT)
------------------------------------------------------------------- -------------------
(clock Po_DAC1_DATCLKIN_P_obj rise edge)
0.000 0.000 r
BUFR_X1Y9 BUFR 0.000 0.000 r FSA_Main_i/selectio_LDV1/inst/clkout_buf_inst/O
net (fo=55, routed) 0.298 0.298 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_in1
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.745 -1.447 r FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.823 -0.624 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.030 -0.594 r FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clkout1_buf/O
net (fo=3, routed) 0.039 -0.555 FSA_Main_i/util_ds_buf_0/U0/BUFGCE_I[0]
BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O)
0.030 -0.525 r FSA_Main_i/util_ds_buf_0/U0/USE_BUFGCE.GEN_BUFGCE[0].BUFGCE_U/O
net (fo=164918, routed) 1.064 0.539 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_in
OLOGIC_X0Y30 ODDR (Prop_oddr_C_Q) 0.221 0.760 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/Q
net (fo=1, routed) 0.000 0.760 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_fwd_out
AR34 OBUFDS (Prop_obufds_I_O) 0.770 1.530 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/obufds_inst/O
net (fo=0) 0.000 1.530 Po_DAC1_DATCLKIN_P
AR34 r Po_DAC1_DATCLKIN_P (OUT)
clock pessimism -0.074 1.456
clock uncertainty 0.148 1.604
output delay -0.170 1.434
-------------------------------------------------------------------
required time -1.434
arrival time 1.266
-------------------------------------------------------------------
slack -0.168
report_timing -setup -to [get_ports PVo_DAC1_DA_P]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
| Date : Fri Feb 9 15:00:06 2018
| Host : SV2104 running 64-bit Service Pack 1 (build 7601)
| Command : report_timing -setup -to [get_ports PVo_DAC1_DA_P]
| Design : FSA_Main_wrapper
| Device : 7vx485t-ffg1761
| Speed File : -2 PRODUCTION 1.12 2014-09-11
------------------------------------------------------------------------------------
Timing Report
Slack (MET) : 0.368ns (required time - arrival time)
Source: FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[1].oddr_inst/C
(falling edge-triggered cell ODDR clocked by CLK_375M_OBJ {rise@0.000ns fall@1.334ns period=2.667ns})
Destination: PVo_DAC1_DA_P[1]
(output port clocked by Po_DAC1_DATCLKIN_P_obj {rise@0.000ns fall@1.334ns period=2.667ns})
Path Group: Po_DAC1_DATCLKIN_P_obj
Path Type: Max at Fast Process Corner
Requirement: 1.334ns (Po_DAC1_DATCLKIN_P_obj rise@2.667ns - CLK_375M_OBJ fall@1.334ns)
Data Path Delay: 1.044ns (logic 1.044ns (100.000%) route 0.000ns (0.000%))
Logic Levels: 1 (OBUFDS=1)
Output Delay: 0.570ns
Clock Path Skew: 0.796ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.269ns = ( 3.936 - 2.667 )
Source Clock Delay (SCD): 0.547ns = ( 1.881 - 1.334 )
Clock Pessimism Removal (CPR): 0.074ns
Clock Uncertainty: 0.148ns ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.027ns
Discrete Jitter (DJ): 0.080ns
Phase Error (PE): 0.093ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock CLK_375M_OBJ fall edge)
1.334 1.334 f
BUFR_X1Y9 BUFR 0.000 1.334 f FSA_Main_i/selectio_LDV1/inst/clkout_buf_inst/O
net (fo=55, routed) 0.298 1.632 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_in1
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.745 -0.113 f FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.823 0.710 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.030 0.739 f FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clkout1_buf/O
net (fo=3, routed) 0.039 0.778 FSA_Main_i/util_ds_buf_0/U0/BUFGCE_I[0]
BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O)
0.030 0.808 f FSA_Main_i/util_ds_buf_0/U0/USE_BUFGCE.GEN_BUFGCE[0].BUFGCE_U/O
net (fo=164918, routed) 1.072 1.880 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_in
OLOGIC_X0Y42 ODDR f FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[1].oddr_inst/C
------------------------------------------------------------------- -------------------
OLOGIC_X0Y42 ODDR (Prop_oddr_C_Q) 0.221 2.102 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[1].oddr_inst/Q
net (fo=1, routed) 0.000 2.102 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/data_out_to_pins_int[1]
BA36 OBUFDS (Prop_obufds_I_O) 0.823 2.924 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[1].obufds_inst/O
net (fo=0) 0.000 2.924 PVo_DAC1_DA_P[1]
BA36 r PVo_DAC1_DA_P[1] (OUT)
------------------------------------------------------------------- -------------------
(clock Po_DAC1_DATCLKIN_P_obj rise edge)
2.667 2.667 r
BUFR_X1Y9 BUFR 0.000 2.667 r FSA_Main_i/selectio_LDV1/inst/clkout_buf_inst/O
net (fo=55, routed) 0.255 2.922 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_in1
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.447 1.475 r FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.759 2.234 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 2.260 r FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clkout1_buf/O
net (fo=3, routed) 0.035 2.295 FSA_Main_i/util_ds_buf_0/U0/BUFGCE_I[0]
BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O)
0.026 2.321 r FSA_Main_i/util_ds_buf_0/U0/USE_BUFGCE.GEN_BUFGCE[0].BUFGCE_U/O
net (fo=164918, routed) 0.796 3.117 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_in
OLOGIC_X0Y30 ODDR (Prop_oddr_C_Q) 0.192 3.309 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/Q
net (fo=1, routed) 0.000 3.309 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_fwd_out
AR34 OBUFDS (Prop_obufds_I_O) 0.627 3.936 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/obufds_inst/O
net (fo=0) 0.000 3.936 Po_DAC1_DATCLKIN_P
AR34 r Po_DAC1_DATCLKIN_P (OUT)
clock pessimism 0.074 4.010
clock uncertainty -0.148 3.862
output delay -0.570 3.292
-------------------------------------------------------------------
required time 3.292
arrival time -2.924
-------------------------------------------------------------------
slack 0.368
#-------------------------------------------------------------------------------------------------------------------------------------------------------
# HIGH SPEED ADC's - 375 MHz Differential Clock
#-------------------------------------------------------------------------------------------------------------------------------------------------------
#LDV1
create_clock -period 2.666 -name Pi_CH2_CLOCK_P_obj -waveform {0.000 1.333} [get_ports Pi_CH2_CLOCK_P_clk_p]
#-------------------------------------------------------------------------------------------------------------------------------------------------------
# High Speed DAC's Clocks - SRS 1 - 17 - 2018 (Forwarded Clock is running at 375MHz)
#-------------------------------------------------------------------------------------------------------------------------------------------------------
create_generated_clock -name Po_DAC1_DATCLKIN_P_obj -source [get_pins FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/C] -divide_by 1 [get_ports Po_DAC1_DATCLKIN_P]
create_generated_clock -name Po_DAC2_DATCLKIN_P_obj -source [get_pins FSA_Main_i/DAC2_LTC2000_0/U0/LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/C] -divide_by 1 [get_ports Po_DAC2_DATCLKIN_P]
#-------------------------------------------------------------------------------------------------------------------------------------------------------
# MMCM Clocks from MMCM are automatically generated, constraint is not necessary here
#-------------------------------------------------------------------------------------------------------------------------------------------------------
create_generated_clock -name CLK_375M_OBJ -source [get_pins FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/clk_in1] -divide_by 1 [get_pins FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/clk_out1]
create_generated_clock -name CLK_250M_OBJ -source [get_pins FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/clk_in1] -divide_by 3 -multiply_by 2 [get_pins FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/clk_out2]
#-------------------------------------------------------------------------------------------------------------------------------------------------------
# High Speed DAC's set_output_delay's - SRS 1 - 17 - 2018
#-------------------------------------------------------------------------------------------------------------------------------------------------------
# Double Data Rate Source Synchronous Outputs
#
# Source synchronous output interfaces can be constrained either by the max data skew
# relative to the generated clock or by the destination device setup/hold requirements.
#
# Setup/Hold Case:
# Setup and hold requirements for the destination device and board trace delays are known.
#
# forwarded _________________________________
# clock __________| |______________
# | |
# tsu_r | thd_r tsu_f | thd_f
# <------>|<-------> <------>|<----->
# ________|_________ ________|_______
# data @ destination XXX__________________XXXXXXXXXXXXXXXX________________XXXXX
#
# Example of creating generated clock at clock output port
# create_generated_clock -name <gen_clock_name> -multiply_by 1 -source [get_pins <source_pin>] [get_ports <output_clock_port>]
# gen_clock_name is the name of forwarded clock here. It should be used below for defining "fwclk".
set fwclk_DAC1 Po_DAC1_DATCLKIN_P_obj; # forwarded clock name (generated using create_generated_clock at output clock port)
set fwclk_DAC2 Po_DAC2_DATCLKIN_P_obj; # forwarded clock name (generated using create_generated_clock at output clock port)
set tsu_r 0.570; # destination device setup time requirement for rising edge (0.570)
set thd_r -0.170; # destination device hold time requirement for rising edge (-0.170)
set tsu_f 0.570; # destination device setup time requirement for falling edge (0.570)
set thd_f -0.170; # destination device hold time requirement for falling edge (-0.170)
set trce_dly_max 0.000; # maximum board trace delay
set trce_dly_min 0.000; # minimum board trace delay
set output_port_DAC1 {PVo_DAC1_DA_P PVo_DAC1_DB_P}; # list of output ports
set output_port_DAC2 {PVo_DAC2_DA_P PVo_DAC2_DB_P}; # list of output ports
# Output Delay Constraints
set_output_delay -clock $fwclk_DAC1 -max [expr $trce_dly_max + $tsu_r] [get_ports $output_port_DAC1];
set_output_delay -clock $fwclk_DAC1 -min [expr $trce_dly_min - $thd_r] [get_ports $output_port_DAC1];
set_output_delay -clock $fwclk_DAC1 -max [expr $trce_dly_max + $tsu_f] [get_ports $output_port_DAC1] -clock_fall -add_delay;
set_output_delay -clock $fwclk_DAC1 -min [expr $trce_dly_min - $thd_f] [get_ports $output_port_DAC1] -clock_fall -add_delay;
set_output_delay -clock $fwclk_DAC2 -max [expr $trce_dly_max + $tsu_r] [get_ports $output_port_DAC2];
set_output_delay -clock $fwclk_DAC2 -min [expr $trce_dly_min - $thd_r] [get_ports $output_port_DAC2];
set_output_delay -clock $fwclk_DAC2 -max [expr $trce_dly_max + $tsu_f] [get_ports $output_port_DAC2] -clock_fall -add_delay;
set_output_delay -clock $fwclk_DAC2 -min [expr $trce_dly_min - $thd_f] [get_ports $output_port_DAC2] -clock_fall -add_delay;
# Report Timing Template
# report_timing -rise_to [get_ports $output_ports] -max_paths 20 -nworst 2 -delay_type min_max -name src_sync_ddr_out_rise -file src_sync_ddr_out_rise.txt;
# report_timing -fall_to [get_ports $output_ports] -max_paths 20 -nworst 2 -delay_type min_max -name src_sync_ddr_out_fall -file src_sync_ddr_out_fall.txt;
In addition, see the attached 1, I think this shows where the data needs to be valid at the DAC inputs. If the data is held longer, after the clock edge, that would still meet the requirements.
Am I doing this correctly?
Would it be better to just put in zero or a small positive value for the hold time? I'm sure the DAC would not mind if the data was held longer than specified, right?
Question
Joshua_S
Hi guys,
I am trying to properly set up the set_output_delay for a source synchronous output from the FPGA to the LTC2000A DAC, see: http://www.kynix.com/Parts/138283/LTC2000ACY-11%23PBF.html
I have 2 DACs so there is DAC1 and DAC2.
I am using a select_io_wizard to set up the output for each DAC.
Here is the datasheet for the LTC2000A-11 DAC, see: http://cds.linear.com/docs/en/datasheet/2000afb.pdf
On page 19 is the timing diagram, where I have set up the DAC to operate as in Figure 2. (DCKI_Q = 0, DCK_TADJ = 000)
From the timing table on page 8, for t11 and t12, setup time t11 = 570, and hold time t12 is -170.
Because the hold time specified in the LTC2000A datasheet is negative, it looks like the data can be released before the clock edge?
I am using a Virtex 7 at 375MHz, xc7vx485tffg1761-2 (active)
The 375MHz clock comes from a high speed ADC, which goes to a MMCM to generate the FPGA system 375MHz clock, where clk_in1 of the clk_wiz_inst is the output of the selectio_wiz input IP that forwards the clock coming from the high speed ADC.
The 375MHz system clock clocks the selectio_wizard output IP for the DACs.
The CLK_375M_OBJ is the source clock for the forwarded clock.The create_clock and create_generated_clock statements are following the timing reports.
In addition, see the attached 1, I think this shows where the data needs to be valid at the DAC inputs. If the data is held longer, after the clock edge, that would still meet the requirements.
Am I doing this correctly?
Would it be better to just put in zero or a small positive value for the hold time? I'm sure the DAC would not mind if the data was held longer than specified, right?
Thanks all.
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