jpeyron

[nasajohnc]

Hi,

 

I'm trying to build the zybo z7 hdmi tutorial. The tcl script starts to run then stops with a locked IP - "design_1_dvi2rgb_1_0"

Why is this locked? How do I unlock it?

When I run IP Status I get this message:

IP 'design_1_dvi2rgb_1_0' recommendation(s):
* Target IP definition 'DVI to RGB Video Decoder (Sink) (1.8)' requires a minor version change. Please review the change log before upgrading the IP.

I don't know what "change log" I'm supposed to review.

My tcl script output is below.

 

Thanks,

John

 

 

 

source create_project.tcl
# set proj_name "HDMI"
# if {[info exists ::create_path]} {
#     set dest_dir $::create_path
# } else {
#     set dest_dir [file normalize [file dirname [info script]]]
# }
# puts "INFO: Creating new project in $dest_dir"
INFO: Creating new project in C:/Xilinx/Vivado/2016.4/HFCS/Zybo-Z7-20-HDMI/proj
# cd $dest_dir
# set part "xc7z020clg400-1"
# set brd_part "digilentinc.com:zybo-z7-20:part0:1.0"
# set origin_dir ".."
# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
# set src_dir $origin_dir/src
# set repo_dir $origin_dir/repo
# create_project $proj_name $dest_dir
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
# set proj_dir [get_property directory [current_project]]
# set obj [get_projects $proj_name]
# set_property "default_lib" "xil_defaultlib" $obj
# set_property "part" $part $obj
# set_property "board_part" $brd_part $obj
# set_property "simulator_language" "Mixed" $obj
# set_property "target_language" "VHDL" $obj
# set_property "corecontainer.enable" "0" $obj
# set_property "ip_cache_permissions" "read write" $obj
# set_property "ip_output_repo" "[file normalize "$origin_dir/repo/cache"]" $obj
# if {[string equal [get_filesets -quiet sources_1] ""]} {
#   create_fileset -srcset sources_1
# }
# if {[string equal [get_filesets -quiet constrs_1] ""]} {
#   create_fileset -constrset constrs_1
# }
# set obj [get_filesets sources_1]
# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
# update_ip_catalog -rebuild
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Xilinx/Vivado/2016.4/HFCS/Zybo-Z7-20-HDMI/repo'.
# add_files -quiet $src_dir/hdl
# add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
# add_files -fileset constrs_1 -quiet $src_dir/constraints
# if {[string equal [get_runs -quiet synth_1] ""]} {
#   create_run -name synth_1 -part $part -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
# } else {
#   set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
#   set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
# }
# set obj [get_runs synth_1]
# set_property "part" $part $obj
# set_property "steps.synth_design.args.flatten_hierarchy" "none" $obj
# set_property "steps.synth_design.args.directive" "RuntimeOptimized" $obj
# set_property "steps.synth_design.args.fsm_extraction" "off" $obj
# current_run -synthesis [get_runs synth_1]
# if {[string equal [get_runs -quiet impl_1] ""]} {
#   create_run -name impl_1 -part $part -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
# } else {
#   set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
#   set_property flow "Vivado Implementation 2015" [get_runs impl_1]
# }
# set obj [get_runs impl_1]
# set_property "part" $part $obj
# set_property "steps.opt_design.args.directive" "RuntimeOptimized" $obj
# set_property "steps.place_design.args.directive" "RuntimeOptimized" $obj
# set_property "steps.route_design.args.directive" "RuntimeOptimized" $obj
# current_run -implementation [get_runs impl_1]
# puts "INFO: Project created:$proj_name"
INFO: Project created:HDMI
# set bd_list [glob -nocomplain $src_dir/bd/*/*.bd]
# if {[llength $bd_list] != 0} {
#   add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
#   open_bd_design [glob -nocomplain $src_dir/bd/*/*.bd]
#   set design_name [get_bd_designs]
#   set file "$origin_dir/src/bd/$design_name/$design_name.bd"
#   set file [file normalize $file]
#   set file_obj [get_files -of_objects [get_filesets sources_1]

1. ]
   #   if { ![get_property "is_locked" $file_obj] } {
   #     set_property "synth_checkpoint_mode" "Hierarchical" $file_obj
   #   }
   #  
   #   # Generate the wrapper
   #   set design_name [get_bd_designs]
   #   add_files -norecurse [make_wrapper -files [get_files $design_name.bd] -top -force]
   #
   #   set obj [get_filesets sources_1]
   #   set_property "top" "${design_name}_wrapper" $obj
   # }
   Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
   Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
   Adding cell -- xilinx.com:ip:axi_vdma:6.2 - axi_vdma_0
   Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_133M
   Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_100M
   Adding cell -- xilinx.com:ip:axis_subset_converter:1.1 - axis_subset_converter_in
   Adding cell -- xilinx.com:ip:axis_subset_converter:1.1 - axis_subset_converter_out
   Adding cell -- xilinx.com:ip:xlconstant:1.1 - xlconstant_0
   Adding cell -- xilinx.com:ip:v_vid_in_axi4s:4.0 - v_vid_in_axi4s_0
   Adding cell -- xilinx.com:ip:v_tc:6.1 - v_tc_in
   Adding cell -- xilinx.com:ip:v_tc:6.1 - v_tc_out
   Adding cell -- xilinx.com:ip:v_axi4s_vid_out:4.0 - v_axi4s_vid_out_0
   Adding cell -- digilentinc.com:ip:axi_dynclk:1.0 - axi_dynclk_0
   Adding cell -- digilentinc.com:ip:dvi2rgb:1.7 - dvi2rgb_1
   Adding cell -- digilentinc.com:ip:rgb2dvi:1.4 - rgb2dvi_1
   Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
   Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_video
   WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_dynclk_0/LOCKED_O(undef) and /rgb2dvi_1/aRst_n(rst)
   WARNING: [BD 41-1731] Type mismatch between connected pins: /dvi2rgb_1/aPixelClkLckd(undef) and /proc_sys_reset_0/aux_reset_in(rst)
   Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
   Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
   Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
   Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - m00_regslice
   Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
   Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - s01_regslice
   Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - s00_regslice
   Successfully read diagram <design_1> from BD file <../src/bd/design_1/design_1.bd>
   open_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 943.668 ; gain = 114.480
   ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'design_1.bd' is locked. Locked reason(s):
   * BD design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
   List of locked IPs:
   design_1_dvi2rgb_1_0

ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.

    while executing
"make_wrapper -files [get_files $design_name.bd] -top -force"
    invoked from within
"if {[llength $bd_list] != 0} {
  add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
  open_bd_design [glob -nocompla..."
    (file "create_project.tcl" line 125)

 

 

[nasajohnc]

I think I got this to build OK (except it doesn't meet timing). I was able to unlock the IP by closing the entire Vivado environment and then re-opening it. I've seen this quirk/flaw in ISE and Vivado before - something won't register or "stick" until you close and re-open the whole program. Thanks.

[jpeyron]

Hi @nasajohnc,

Welcome to the forums. I am glad you were able to get the project to load and generate a bitstream. I believe the time issues can be ignored in this case. Let us know if the project does not run.

thank you,

Jon