I want to use lvds clock for system generator

[hatas71]

Hi 

I am using Matlab 2017b to generate vhdl code. I have genesys 2 board and I can use only AD18 as a clock. This clock is designed for OTG communication. In the data sheet it looks 26.000 Hz. However when I load bit file to Genesys 2 board, AD18 clock pretents as 60.000 Hz. I want to learn why like this and want to use LVDS clock AD12 on my design.

I have attached one sample. Please help!

Best regards, Hasan 

 

 

new1.slx

[jpeyron]

Hi @hatas71,

Welcome to the forums. We do not have matlab or experience with matlab so i would not be able to help with Matlab. In regards to AD18, this the USB_OTG_CLK not the USB_OTG_RCLK and is connected to the clock on IC5 on page 6 of the schematic here. This is why you are getting a different clock than expected. As far as I can see the USB_OTG_RCLK is not accessible by the fpga. What are you trying to accomplish in general? Here is the resource center for the genesys 2 that has demo's, tutorials and board information that might be helpful. 

thank you,

Jon

[hatas71]

Hi @jpeyron

Thanks for your answer. It's OK with AD18 pin. I have attached xpr file and its Simulink screenshot. I am wondering how to change AD18  with AD12. In general, I want to drive DC motor.

Best regards, Hasan

 

new1.xpr

[jpeyron]

Hi @hatas71,

Unfortunately, we do not have Simulink  experience. Hopefully other community members will have some input for you. Have you tried reaching out to Matlabs support?

thank you,

Jon