Top Level Port error

[newkid_old]

I'm trying to implement a DDR output module that will serve as my ADC simulator.  I have synthesized design but received this error when trying to implement:

[Opt 31-1] OBUFDS design_1_i/util_ds_buf_0/U0/USE_OBUFDS.GEN_OBUFDS[0].OBUFDS_I O pin is not connected to a top-level port.

Can anyone point me in a direction to fix this issue please?

 

[jpeyron]

Hi @newkid_old,

I am not very familiar with this type of error. Here is a xilinx form thread that might be helpful.  Did you mean to have the adc_clk_p an adc_clk_n connected to opposite pins on the clocking wizard?

thank you,

Jon  

[newkid_old]

Thanks for the catch on the channel flop. 

 

[jpeyron]

Hi @newkid_old,

It looked like my forum link did not show. Here is the forum thread i was talking about.

cheers,

Jon