PmodKypad Issue

[Jaskaran Sandhu]

In PmodKypad VHDL example code, the top module contains two components Decoder and Display Controller.

How the value of sclk is taken in decoder component. Please let me know about on what basis values assigned and initialized to sclk. Why 20 bits are taken not any other value. 

 

PmodKYPD.txt

[jpeyron]

Hi @Jaskaran Sandhu,

The port map in PmodKYPD (top module) connects the clock from the PmodKYPD module to the Decoder module. The clk in the PmodKYPD (top module) is constrained to the system clock in the top of the ucf file that is attached below. Could you be more specific about the 20 bits? FPGA4Fun is a great site for learning more about VHDL.

thank you,

Jon

Nexys3_Master.ucf