how many pins are dedicated for clock in nexys 4 ddr artix 7 xc7a100t-csg324

[Ajeeth]

Hi, 

Can anyone tell me how many pins are dedicated for internal clock in nexys 4 ddr. which pin provides 450Mhz clock frequency.

waiting for kind replies. 

Thank you

[jpeyron]

Hi @Ajeeth,

My understanding is that the 450 MHz is the maximum clock that the XC7A100T-1CSG324C can provide. There is a 100 MHz clock as shown in the schematic on page 7 on the bottom left. This is described in the reference manual in section 6 Oscillators/Clocks. You can use the xdc to access the 100 MHz clock as shown below. Then you can manipulate the clock in verilog/VHDL to get to the desired frequency. You can also use the clock wizard(recommended) to do this as well.

## Clock signal
#set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];

cheers,

Jon