Pmod as input and output GPIO

[macornil]

Hi all,

I'm currently playing with the pmod's of a Zybo Z7-20 (revB) and I'm trying to use the pins of the JD pmod as simple GPIO input and output (I want to be able to configure the direction of the pin from the software).
First, I tried to use the PmodGPIO IP (configured with 'jd' board interface) and the 'Zybo-Z7-Master.xdc' constraints file from from Digilent's github repository. Everything works, except that the pin 1 (T14) and 2 (T15) seems to be swapped as well as pin 3 (P14) and pin 4 (R14)... I tried to inverse the package pin name in the constraint file, no success... I don't have this problem if I use an other pmod header, thus I think it's a bug in the IP...

I also tried to configure the 'board interface' of the IP with the 'custom' option but it fails with a 'place_design ERROR'... Same if I try to use the AXI-GPIO IP from Xilinx.
I think it's because of the tri-state (need an IOBUF) but I don't know how to fix this...

Any idea ?

Thanks,

Martin

[jpeyron]

Hi @macornil,

So you change the name of the pin in the XDC like I have done in the below code.

##Pmod Header JD                                                                                                                  
#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33     } [get_ports { jd_pin1_io }]; #IO_L5P_T0_34 Sch=jd_p[1]                  
#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33     } [get_ports { j jd_pin2_io }]; #IO_L5N_T0_34 Sch=jd_n[1]                 
#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33     } [get_ports { jd_pin3_io}]; #IO_L6P_T0_34 Sch=jd_p[2]                  
#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33     } [get_ports { jd_pin4_io}]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]             
#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33     } [get_ports {  jd_pin7_io }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]            
#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33     } [get_ports { jd_pin8_io }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]            
#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33     } [get_ports {  jd_pin9_io }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]             
#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33     } [get_ports { jd_pin10_io }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]    

cheers,

Jon

 

[jpeyron]

Hi @macornil,

I verified that there was an issue with the pin assignments for the Pmod Port JD on the Zybo-Z7-20. The P and N pins needed to be swapped for Pmod Port JD. I fixed this issue that was in the board files. Please re-download the board files and this issue should be fixed. When you want to assign the pins not using the board files i.e JA,Jb,JC... you would right click on the pmod out port on the IP core and click on make external. Then once you have created a wrapper for your design you would constrain the pins that the wrapper makes for those external pins for the IP core with the xdc.

cheers,

Jon

[macornil]

Hi @jpeyron,

Thank you for the quick reply.

Great, now it works correctly with the updated board files, thank you!

I also found what was the problem when I use the constraints file (with 'custom' option in the IP core). I used the constraints file provided on the github repo and I simply uncommented the constraints for the JD Pmod. But, the problem is that the pins generated by Vivado in the HDL wrapper are independent inout ports in contrary to the vector of pins declared in the constraints file.
If I create the port in the design with "make external", rename it 'JD' and then declare in the constraints file the pins with the names jd_pin1_io, jd_pin2_io, jd_pin3_io, jd_pin4_io, jd_pin7_io, jd_pin8_io, jd_pin9_io, jd_pin10_io instead of the vector form, it works.
Is it possible to keep the vector declaration in any way, instead? Would be better...

If I use the AXI-GPIO IP core from Xilinx, I have to declare them with as a vector named name 'jd_tri_io'.

Thank you for your time,

Martin