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Tamper resistent design for CMOD A7




I want to know how to develope a tamper resistent design for my CMOD A7 board.
it seems that encrypted bitstream tecnique can't be used with this board because i can't program eFuse register and can't connect a battery-backed RAM to store the key. 

So i have read that there are some active features as JTAG Monitor and JTAG Disable. I have found only a template but i don't have idea how to use in my design. As i think i undestad seems that JTAG Disable can breaks the jtag chain to disable the read back and there is no way to stole my design. It's right? And, how can i do this?

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Hi @smarano,

I have no experience in disabling the JTAG. Hopefully on of the more experience community members will have some input for you. I would suggest to look at the 7 Series FPGAs Configuration User Guide that discusses this process. I would also suggest to reach out to Xilinx support here for their input as well. 



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