Just got the ArtyZ7 yesterday. I have been using Xilinx FPGA's many years ago, recently been using Actel. The xilinx design suite has certainly changed since i last used it. Wanting to dabble with creating a FPGA design with a CPU inside. Good experience for home use, but may also come in handy in my line of work.
So to get started I downloaded the hdmi-out demo. Got the latest project using the Git system, ran the tcl script, copied in libraries, click build.
I get this error:-
[DRC NSTD-1] Unspecified I/O Standard: 7 out of 145 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: HDMI_DDC_scl_i, HDMI_DDC_scl_o, HDMI_DDC_scl_t, HDMI_DDC_sda_i, HDMI_DDC_sda_o, HDMI_DDC_sda_t, and HDMI_HPD_tri_i[0].
The only constraints file i have is attached.
Do i need to fudge something to get it to work, or import another constraints file from somewhere?
Question
TransAmDan
Just got the ArtyZ7 yesterday. I have been using Xilinx FPGA's many years ago, recently been using Actel. The xilinx design suite has certainly changed since i last used it. Wanting to dabble with creating a FPGA design with a CPU inside. Good experience for home use, but may also come in handy in my line of work.
So to get started I downloaded the hdmi-out demo. Got the latest project using the Git system, ran the tcl script, copied in libraries, click build.
I get this error:-
[DRC NSTD-1] Unspecified I/O Standard: 7 out of 145 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: HDMI_DDC_scl_i, HDMI_DDC_scl_o, HDMI_DDC_scl_t, HDMI_DDC_sda_i, HDMI_DDC_sda_o, HDMI_DDC_sda_t, and HDMI_HPD_tri_i[0].
The only constraints file i have is attached.
Do i need to fudge something to get it to work, or import another constraints file from somewhere?
Many Thanks in advance.
ArtyZ7_B.xdc
Link to comment
Share on other sites
4 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.