the Schematic does not match the Ref Manual as per the full pin outs, some do, but in this example where the 4 digit 7 seg display as per the RM designates pin 25 on the CPLD as the CA Common Anode, connection; however, on the schematic pin 56 is designated as a hard connection for CA
Can you verify there is an error in one of the documents and can you provide a UCF file, config file for the Base full project file for VHDL or Verilog.
Answer
The correct pin number should be the one at the schematic which is pin 56. Our application engineering team will fix the error in the reference manual. In the meantime, please refer to the schematic or the silkscreen on the board to find out the right pin when you make the constraint file.
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Alex
Hi, I get a question from the distributor about the documentation error we have. See my answer.
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