ARTY S7 microblaze

[Cord]

Hi,

has anyone been successful designing a simple microblaze system in Vivado 2017.2 (block diagram)?

Trying to do this (taking Arty - Getting started with Microblaze as template) the mig block always is a show stopper.

The autoconnect always ends with the same error message (see below), trying to configure mig manually does not work too.

 

Thanks,

Cord

[jpeyron]

Hi @Cord,

I have been getting the same error when I try to add the ddr3 to a block design. I will research this next week and get a response for you about the ddr3. In regards to getting a microblaze project running on the Arty-s7-50. Here is the base uc project that a mictoblaze/sdk project. When you download the project you must also download the vivado library here and put the contents in the folder located Arty-S7-50-base-uc/repo/vivado-library/ . 

cheers,

Jon

[tomclancy]

On 9/30/2017 at 1:13 AM, Cord said:

Hi,

has anyone been successful designing a simple microblaze system in Vivado 2017.2 (block diagram)?

Trying to do this (taking Arty - Getting started with Microblaze as template) the mig block always is a show stopper.

The autoconnect always ends with the same error message (see below), trying to configure mig manually does not work too.

 

Thanks,

Cord

Hi @Cord, I did not get any error, well i was trying to add mig and microblaze and was successful though, but somehow i'm unable to fix the usb uart ip one, the rev b schematics does not have the usb schematics, that page is intentionally left empty. Did you add the usb uart ip to it?

[jpeyron]

Hi @tomclancy and @Cord,

I have been researching this issue along with reaching out to my co-workers to get more input into this issue. @tomclancy, the page you are referring to on the schematic has the programming solution and is considered proprietary. Unfortunately we would not be able to give you this information. Here and here are project that should help with using the PS for now. You need to use uses git clone --recursive when downloading these projects from GitHub.

cheers,

Jon

[sbobrowicz]

3 hours ago, jpeyron said:

Unfortunately we would not be able to give you this information. Here and here are project that should help with using the PS for now.

Little correction, no PS (Zynq processing system) in the Arty S7. It will help them with microblaze and the MIG

If I had to guess, I would bet that this has to do with a bug in the new "AXI Smart connect" ip that Xilinx is now instantiating when using autoconnect. 

For now, I would recommend using the Arty-S7-50-base-rt project that Jon linked to above as a starting point for your design. If you don't want to bother with git, you can download it from the "releases" tab in github (just be sure not to download it using the "Download ZIP" button, that will not work). 

[tomclancy]

On 10/5/2017 at 4:25 PM, tomclancy said:

Hi @Cord, I did not get any error, well i was trying to add mig and microblaze and was successful though, but somehow i'm unable to fix the usb uart ip one, the rev b schematics does not have the usb schematics, that page is intentionally left empty. Did you add the usb uart ip to it?

 

11 hours ago, sbobrowicz said:

Little correction, no PS (Zynq processing system) in the Arty S7. It will help them with microblaze and the MIG

If I had to guess, I would bet that this has to do with a bug in the new "AXI Smart connect" ip that Xilinx is now instantiating when using autoconnect. 

For now, I would recommend using the Arty-S7-50-base-rt project that Jon linked to above as a starting point for your design. If you don't want to bother with git, you can download it from the "releases" tab in github (just be sure not to download it using the "Download ZIP" button, that will not work). 

This is the schematics, attached below the text i was talking about, actually the circuit consist of a dual port USB, one of them is a 245FIFO, other one is rs232 port.

When i build a microblaze based memory controller design on the arty s750 board where should i connect the uart signals is this constraint information correct?

##USB-UART Interface

#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in

Need to do reverse engineering. LOL! Do not know what is proprietary, USB interface or the Xilinx FPGA Bank 16. 

 

[jpeyron]

Hi @tomclancy,

Here is our XDC file for the Arty-S7-50 which is linked from our resource page for the Arty-S7-50 here. The XDC file contains constrains for the UART. I have also included a screen shot of bank 14 of the schematic which shows pins R12 and V12. You should use the below constraints for the rx and tx of the uart.

#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out

#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in

The programming solution on page 9 is proprietary, hence the 'This page is left intentionally blank".

 

 

cheers,

Jon

[tomclancy]

On 10/6/2017 at 6:06 PM, tomclancy said:

On 10/6/2017 at 6:32 AM, sbobrowicz said:

Little correction, no PS (Zynq processing system) in the Arty S7. It will help them with microblaze and the MIG

If I had to guess, I would bet that this has to do with a bug in the new "AXI Smart connect" ip that Xilinx is now instantiating when using autoconnect. 

For now, I would recommend using the Arty-S7-50-base-rt project that Jon linked to above as a starting point for your design. If you don't want to bother with git, you can download it from the "releases" tab in github (just be sure not to download it using the "Download ZIP" button, that will not work). 

 

On 10/6/2017 at 11:42 PM, jpeyron said:

Hi @tomclancy,

Here is our XDC file for the Arty-S7-50 which is linked from our resource page for the Arty-S7-50 here. The XDC file contains constrains for the UART. I have also included a screen shot of bank 14 of the schematic which shows pins R12 and V12. You should use the below constraints for the rx and tx of the uart.

#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out

#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in

The programming solution on page 9 is proprietary, hence the 'This page is left intentionally blank".

 

 

cheers,

Jon

Thanks sbobrowicz and Jon. Was successful in order to perform few tests on the board, it is really good. 

Cheers! 

 

[jpeyron]

Hello everyone,

I am working with Xilinx on this issue through their support channels about the Arty-S7-50 and the issue with the MIG. I am hoping to hear more about this issue early next week.

thank you,

Jon

[jpeyron]

Hello everyone,

The Xilinx support was able to duplicate this issue. After some research Friday and over the weekend they found that it is a problem with Xilinx's WebPack install and Spartan-7 Devices.  They have filed an internal CR to resolve this issue. On a side note, they were able to resolve the runtime error by upgrading the install to Design Edition. 

thank you,

Jon

[jpeyron]

Hello everyone,

I confirmed that upgrading to the Design edition resolved the runtime issue with the MIG. A screen shot of this is attached below. You can upgrade Vivado to the design Edition and use the Design edition without needing the design license as long as you are not targeting a device that required the design license for use.

cheers,

Jon