Vivado 2016.2 ERROR: [Xicom 50-38] xicom: Core access failed

[new_user]

Hi

I have a design which synthesizes and implements without any timing errors. But when I trigger the ILA after dumping the bitstream, this error comes up-

ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.

ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.

ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.

ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.

ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.

ERROR: [Labtools 27-3176] hw_server failed during internal command.

Resolution: Check that the hw_server is running and the hardware connectivity to the target

 

The design in implemented on Virtex-7vc707

I have an FMC card as a part of design. Things tried-

1. Changing the FMC port

2. Reducing number of probes from ILA

3. Making the design smaller

4. Checked the IR length of JTAG

 

None of these have worked out. I have tried a lot of variations of the design, in some designs I get the error immediately after triggering ILA and in others, it comes up after 4-5 triggers.
I have been struggling with this issue for some while now, please suggest what could be wrong.

[jpeyron]

Hi @new_user,

Welcome to the forum! Unfortunately, I do not have a lot of experience with the ILA and no experience with the Virtex-7vc707. You also reached out to the Xilinx forums which is what I would have suggested in this case. It looks like your question on the Xilinx forums here is pointing you to checking the power supply rails and potentially to get a bigger power supply.

cheers,

Jon