Nexys_Video_Vivado2014_PmodAD1

[Miguel]

Dear Collegues!

I tried to find an answer for my question but I've found nothing...

I try to create program in the VHDL. I use PmodAD1, I did Sysclk (16 kHz), Cs (1kHz) signals. I se on the oscilloscope all signalls (Sysclk, Cs and D0).

The question is: how to obtain std_logic_vector variable and the integer value of the obtained variable?

If it was described, please, give me a link...

 

Code is bellow.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pmod_ad1 is
    Port ( sysclk     : in  STD_LOGIC;
           ja         : inout STD_LOGIC_VECTOR(7 downto 0);
           led   : out STD_LOGIC_VECTOR(7 downto 0)
           );
end pmod_ad1;

architecture Behavioral of pmod_ad1 is

    signal CLK_PSC     : STD_LOGIC_VECTOR(12 downto 0);
    signal CS_PSC      : STD_LOGIC_VECTOR(5 downto 0);
    signal PSC      : STD_LOGIC_VECTOR(15 downto 0);
    signal data1_sr    : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
    signal temp1    : integer;
    signal temp2    : integer;
    signal m    : integer :=data1_sr'high-1;
    signal l    : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
    signal r_counter_data             : STD_LOGIC_VECTOR(3 downto 0);
    
    signal  check : STD_LOGIC;

    signal clk : STD_LOGIC := '0';
    signal cs : STD_LOGIC := '0';
begin

process(sysclk) 
    begin
        if rising_edge(sysclk) then
            if CLK_PSC < "110000110100" then
                CLK_PSC <= CLK_PSC + 1;
                else
                CLK_PSC <= (others => '0');
                clk <= not clk;
            end if;
        end if;
end process;

process(clk)
    begin
        if rising_edge(clk) then
            if CS_PSC < "1111" then
                CS_PSC <= CS_PSC + 1;
                cs <= '0'; 
                else
                CS_PSC <= (others => '0');
                cs <= '1';
            
            
                --temp1 <= to_integer(unsigned(data1_sr));
                --temp2 <= temp1 / 20;
                --l <= std_logic_vector(to_unsigned(temp2, l'length));
                
            end if;
        end if;    
end process;

process(sysclk) 
    begin
        if rising_edge(sysclk) then
            if PSC < "1001110001000" then
                PSC <= PSC + 1;
                else
                PSC <= (others => '0');

                
            end if;
        end if;
end process;

   led <= l;
   ja(4)  <= cs;
   ja(7) <= clk;
   ja(0)<=ja(4);
   ja(1)<=ja(5);
   ja(3)<=ja(7);
end Behavioral;

[jpeyron]

Hi @Miguel,

Welcome to the forums! @hamster has a completed project for the PmodAD1 in VHDL here. It was done for the Basys 3 so you need to use the Nexys Video's xdc instead.

cheers,

Jon