Danh Doan Posted May 10, 2017 Share Posted May 10, 2017 Hi everyone, I'm trying to interface with QDRII+ and I use NetFPGA-1G CML Kintex-7 I have done the simulation, it works just fine, however when I implement to the real board, the calibration is failed. I have 2 questions: Do I need to use exact frequency for sys_clk_p/n (it requires 450.045 MHz)? In the NetFPGA board, I just see 1 pair system_clk_p/n (200MHz), I'm supposed to use it as clk_ref_p/n, what should I use for sys_clk_p/n(450.045MHz) Thanks in advance. Link to comment Share on other sites More sharing options...
jpeyron Posted May 10, 2017 Share Posted May 10, 2017 Hi @Danh Doan, You need to use the NetFPGA forums for support on the interfacing the NetFPGA-1G CML and the QDRII. If you are not already registered, you can use the registration link located on the "Getting Started" page here. Once registered, you should use the NetFPGA forum to post your question. thank you, Jon Link to comment Share on other sites More sharing options...
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Danh Doan
Hi everyone,
I'm trying to interface with QDRII+ and I use NetFPGA-1G CML Kintex-7
I have done the simulation, it works just fine, however when I implement to the real board, the calibration is failed.
I have 2 questions:
Thanks in advance.
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