So I must admit I'm more a software guy than a hardware guy, so hopefully this is an easy one. I want to read in bits on pins at 8.192 MHz, buffer them, and send them out on Ethernet via UDP. Ethernet requires 50 MHz and 25 MHz (not a multiple of 8.192 MHz).
I have everything working in simulation, and even in the hardware realm by using the Ethernet clock for my fake data (I just have a counter that counts to N*(25/8.192) instead of counting to N before sending the packet, sending N bits). It's based off the excellent ArtyEthernetTX project which has this for line 1 of the XDS
But I got errors saying it was "poor placement routing" and the solution from Xilinx is to move it to a clock-capable in. Unfortunately, I can't find any reference in the Arty manual to a clock capable pin! I tried the clock pin for the SPI header, but that had the same error.
I figure there's three solutions
1) Find a clock capable pin (there has to be one, right?) and you guys can help me find one!
2) Since Arty has a 100MHz "internal" clock, somehow tap that in my VHDL file and use E3 for my external clock
3) Wrap my whole thing in a Custom IP, duplicate every input and output to the wrapper, connect my external clock to pin E3, use Clocking Wizard to generate 100 MHz.
I think 3 will work, but it just seems like overkill - certainly you can drive a development board with an external clock and still be able to send data out via Ethernet.
Thank you all for any help! I hope I'm missing something obvious here
Question
rnelsonee
So I must admit I'm more a software guy than a hardware guy, so hopefully this is an easy one. I want to read in bits on pins at 8.192 MHz, buffer them, and send them out on Ethernet via UDP. Ethernet requires 50 MHz and 25 MHz (not a multiple of 8.192 MHz).
I have everything working in simulation, and even in the hardware realm by using the Ethernet clock for my fake data (I just have a counter that counts to N*(25/8.192) instead of counting to N before sending the packet, sending N bits). It's based off the excellent ArtyEthernetTX project which has this for line 1 of the XDS
# Clock signal set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk100MHz] create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk100MHz]
So I tried to add a new clock with an I/O pin, like
set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { sample_clock }]; #IO_0_14 Sch=ck_io[30]
But I got errors saying it was "poor placement routing" and the solution from Xilinx is to move it to a clock-capable in. Unfortunately, I can't find any reference in the Arty manual to a clock capable pin! I tried the clock pin for the SPI header, but that had the same error.
I figure there's three solutions
1) Find a clock capable pin (there has to be one, right?) and you guys can help me find one!
2) Since Arty has a 100MHz "internal" clock, somehow tap that in my VHDL file and use E3 for my external clock
3) Wrap my whole thing in a Custom IP, duplicate every input and output to the wrapper, connect my external clock to pin E3, use Clocking Wizard to generate 100 MHz.
I think 3 will work, but it just seems like overkill - certainly you can drive a development board with an external clock and still be able to send data out via Ethernet.
Thank you all for any help! I hope I'm missing something obvious here
Link to comment
Share on other sites
9 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.