Regarding implementation of queues in vivado

[Aditya Gedela]

Can we use inbuilt queues in Vivado?

I tried using them and ended up with lot of errors while synthesis...

So Can anyone please give me some example based on the implementation of queues in vivado?

 

Thanks in Advance....

[D@n]

@Aditya Gedela,

Queue's, not FIFO's?

You should be able to use any simple Xilinx IP package within Vivado.

Can you explain more of what you are struggling with, and what you wish to accomplish?

Dan

[jpeyron]

Hi @Aditya Gedela,

Here is a Xilinx forum thread that deals with dynamic queues which has a coded example on the bottom of the thread. In the thread a Xilinx moderator states that they do support queues with Vivado simulator but not with synthesis.

cheers,

Jon

[D@n]

@Aditya Gedela,

If you can build a FIFO, you can build a Queue.  They're just not all that different, and they are not all that difficult either.  Queue's just read from the most-recently written end of memory.  If you build your own, I would suggest you use a single clock rather than a pair of clocks, one for read and one for write--as is commonly done with FIFOs.  On the other hand, if your goal is to use a pre-built core, then ... I'm still not sure what answer more to give.

If your goal is to use HLS (Xilinx's version of C to Verilog translation), then ... let me highly discourage you from doing so.    FPGA design is very different from computer programming, and as a beginner, you need to learn that difference before trying to build your typical programming constructs.

Have you looked at fpga4fun.com?  It's a great beginner site.

Just my two cents.

Dan