Questions for NEXYS4 DDR eval board

[silverwolfman]

Hi Everyone,

I am developing a design based on ISE 14.7, Artix-7 CSG324 NEXYS4 eval board.  For testing purpose, I wrote a simple clock divider code as following, but the compiler keeps warning me: Line 31(red line): Result of 32-bit expression is truncated to fit in 1-bit target.  The RTL schematic looks the same as I expected, If ignore the warning and program the eval board, clock frequency wouldn't change when SW0 - SW3 input changed.  

I wonder if it is because of compatible issue for the compiler(most people use vivado for artix-7)?  But on the Xilinx website it says the ISE will support Artix-7CX7A100T. 

Please let me know if you guys have any suggestions, Thanks ahead.

module CLKDIVIDER(
    input clk_i,
     input rst_n_i,
    input [3:0] divider_i,
    output clk_o
    );
     
     reg [15:0] clk_cnt;
     reg clk_o_s;
     
    assign clk_o = (rst_n_i == 1'b0)? 0 : clk_o_s;    
    always @ (posedge clk_i) begin
        if (rst_n_i == 1'b0) begin
            clk_cnt <= 0;
        end
        else begin
            clk_cnt <= clk_cnt + 1'b1;    
            clk_o_s <= clk_cnt[ divider_i];
        end
        
    end 

endmodule

 

Updates:  The code when through now without warning, but after burn the code into NEXYS4 ddr board, it is not generating the output when I change the input.

 

 

Test.zip

[D@n]

Gosh, that one's got me stumped as well.  That should work.

Suppose you instead define clk_cnt as "reg clk_cnt [0:15];" instead.  Does that change anything?

Dan

[artvvb]

@D@n

I believe in verilog that will let you only access one bit per clock cycle, so the previous line (30?) will then break.

@silverwolfman

Perhaps try the following in the place of the red line?

clk_o_s <= clk_cnt >> divider_i;

Hope this helps,

Arthur

[hamster]

Something like this maybe? (I don't use Verilog)...

if(clk_cnt[ divider_i] == 1'b1)

    clk_o_s <= 1'b1;

else

    clk_o_s <= 1'b0;

;

[lvoudour]

@silverwolfman

Synthesized your code in 14.7 (for a spartan 6 device, but it shouldn't matter). The "Result of 32-bit expression is truncated to fit in 1-bit target" is on line 11 of the code you posted here (not line 31)

assign clk_o = (rst_n_i == 1'b0)? 0 : clk_o_s;

but that's because the 0 assignment is treated as an integer. If you change it to:

assign clk_o = (rst_n_i == 1'b0)? 1'b0 : clk_o_s;

the warning goes away. Your synthesis report says line 31 because the CLKDIVIDER.v in the zip file also contains a comments header which pushes the aforementioned line to 31

Simulation in modelsim also works as expected, just a note though:
The resulting frequency won't be Fclk / divider (if that's what you intended) but Fclk / 2^(divider+1)

Regards,
Lymperis

 

[silverwolfman]

4 hours ago, lvoudour said:

lsim also works as expected, just a note though:
The resulting frequency won't be Fclk / divider (if that's what you intended) but Fclk / 2^(divider+1)

Regards,
Lymperis

 

Thank you Ivoudour,

The Warning goes away.  you are correct, it is a Fclk / 2^(divider+1) divider, the compiling succeed without the warning.

There is another issue when I try to burn the program into the NEXYS 4 board, it is my first time to use this eval board. It still not working as I slide the sw changing the input.  I basically just use the "Configure Target Device" and program the device with .bit file generated from the design(when i program the chip, it went through without error message, so I assume it is not a chip or board damage).  I have also tried the  Adept software and this is not working as well.  I use to have a CPLD eval board and this program process is working fine under ISE webpack without any issue.