constraints file for seven segment nexys4

[reda9]

hi guys ; 

please i want to use seven segment in nexys 4 board and i have a error i think from the constraints file i'm not understand how to use constraints file to define the seven segment

this is the program and constraints file 

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sev_seg is
    Port (
        CLKIN : in std_logic;
             an3 : inout std_logic;
             an2 : inout std_logic;
             an1 : inout std_logic;
             an0 : inout std_logic;
             seg : out std_logic_vector(6 downto 0));
end sev_seg;

architecture Behavioral of sev_seg is
signal CTR : STD_LOGIC_VECTOR(12 downto 0);  
begin
Process (CLKIN)
begin
  if CLKIN'event and CLKIN = '1' then
    if (CTR="0000000000000") then
      if (an0='0') then 
        an0 <= '1';     
        seg <= "0101011";             -- the letter n
        an1 <= '0';
      elsif (an1='0') then 
        an1 <= '1';          
        seg <= "0101011";             -- the letter n
        an2 <= '0';
      elsif (an2='0') then 
        an2 <= '1';     
        seg <= "0001000";             -- the letter A
        an3 <= '0';
      elsif (an3='0') then 
        an3 <= '1';
        seg <= "0000110";             -- the letter E
        an0 <= '0';
      end if;
    end if;
    CTR<=CTR+"0000000000001";
    if (CTR > "1000000000000") then
      CTR<="0000000000000";
    end if;
  end if; -- CLK'event and CLK = '1' 
End Process;

end Behavioral;

------------------------------------------------------------------------------------------------------

constraints file

##7 segment display
##Bank = 34, Pin name = IO_L2N_T0_34,                        Sch name = CA
set_property PACKAGE_PIN L3 [get_ports {seg[0}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
##Bank = 34, Pin name = IO_L3N_T0_DQS_34,                    Sch name = CB
set_property PACKAGE_PIN N1 [get_ports {seg[1]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
##Bank = 34, Pin name = IO_L6N_T0_VREF_34,                    Sch name = CC
set_property PACKAGE_PIN L5 [get_ports {seg[2]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
##Bank = 34, Pin name = IO_L5N_T0_34,                        Sch name = CD
set_property PACKAGE_PIN L4 [get_ports {seg[3]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
##Bank = 34, Pin name = IO_L2P_T0_34,                        Sch name = CE
set_property PACKAGE_PIN K3 [get_ports {seg[4]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
##Bank = 34, Pin name = IO_L4N_T0_34,                        Sch name = CF
set_property PACKAGE_PIN M2 [get_ports {seg[5]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
##Bank = 34, Pin name = IO_L6P_T0_34,                        Sch name = CG
set_property PACKAGE_PIN L6 [get_ports {seg[6]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

##Bank = 34, Pin name = IO_L16P_T2_34,                        Sch name = DP
set_property PACKAGE_PIN M4 [get_ports dp]                            
    set_property IOSTANDARD LVCMOS33 [get_ports dp]

##Bank = 34, Pin name = IO_L18N_T2_34,                        Sch name = AN0
set_property PACKAGE_PIN N6 [get_ports {an0}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {an0}]
##Bank = 34, Pin name = IO_L18P_T2_34,                        Sch name = AN1
set_property PACKAGE_PIN M6 [get_ports {an1}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {an1}]
##Bank = 34, Pin name = IO_L4P_T0_34,                        Sch name = AN2
set_property PACKAGE_PIN M3 [get_ports {an2}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {an2}]
##Bank = 34, Pin name = IO_L13_T2_MRCC_34,                    Sch name = AN3
set_property PACKAGE_PIN N5 [get_ports {an3}]                    
    set_property IOSTANDARD LVCMOS

##7 segment display
##Bank = 34, Pin name = IO_L2N_T0_34,                        Sch name = CA
set_property PACKAGE_PIN L3 [get_ports {seg[0}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
##Bank = 34, Pin name = IO_L3N_T0_DQS_34,                    Sch name = CB
set_property PACKAGE_PIN N1 [get_ports {seg[1]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
##Bank = 34, Pin name = IO_L6N_T0_VREF_34,                    Sch name = CC
set_property PACKAGE_PIN L5 [get_ports {seg[2]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
##Bank = 34, Pin name = IO_L5N_T0_34,                        Sch name = CD
set_property PACKAGE_PIN L4 [get_ports {seg[3]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
##Bank = 34, Pin name = IO_L2P_T0_34,                        Sch name = CE
set_property PACKAGE_PIN K3 [get_ports {seg[4]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
##Bank = 34, Pin name = IO_L4N_T0_34,                        Sch name = CF
set_property PACKAGE_PIN M2 [get_ports {seg[5]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
##Bank = 34, Pin name = IO_L6P_T0_34,                        Sch name = CG
set_property PACKAGE_PIN L6 [get_ports {seg[6]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

##Bank = 34, Pin name = IO_L16P_T2_34,                        Sch name = DP
set_property PACKAGE_PIN M4 [get_ports dp]                            
    set_property IOSTANDARD LVCMOS33 [get_ports dp]

##Bank = 34, Pin name = IO_L18N_T2_34,                        Sch name = AN0
set_property PACKAGE_PIN N6 [get_ports {an0}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {an0}]
##Bank = 34, Pin name = IO_L18P_T2_34,                        Sch name = AN1
set_property PACKAGE_PIN M6 [get_ports {an1}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {an1}]
##Bank = 34, Pin name = IO_L4P_T0_34,                        Sch name = AN2
set_property PACKAGE_PIN M3 [get_ports {an2}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {an2}]
##Bank = 34, Pin name = IO_L13_T2_MRCC_34,                    Sch name = AN3
set_property PACKAGE_PIN N5 [get_ports {an3}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {an3}]

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[jpeyron]

Hi reda9,

First off, it looks like you are trying to constrain the same pins twice. So that would be one issue also could you post the errors that you are getting.

thank you,

Jon