Implementation failed without error or critical warning

[vvk]

The  design containing traffic generator ,aurora 64/66 b,Axi chip to chip IPs is synthesized successfully but the implementation  is failing with out showing any error/ crictical warning. what could be the reason? please help me in resolving this issue.

[jpeyron]

Hi vvk,

Have you looked here for possible solutions to this issue?

cheers,

Jon