I'm developing TCP application based on the LWIP RAW and I'm stucked with a strange behaviour with similar hdl design and same application code on two different hw platforms - the trainer board Nexys 4 DDR and evaluation board Xilinx VC707
My problem is that everything works on VC707 board (for now).
My application code is a TCP server what sends continually data to connected client. I was testing this code thoroughly so it handles every possible situations (reset, abort flags, unplugged cable, connecting more clients...), dumping LWIP stats to check if there are some memory leaks and another stuff. I left this board to do its job for couple of hours/days without a problem. It just lives like I want.
The HDL design is simplified reference design for VC707 (Microblaze, DMA, AXI Ethernet...). The softprocessor is set for best performance (optional settings for instructions, cache and stuff).
So only difference is ethernet part - Axi EthernetLite and MII to RMII cores. VC707 has the gigabit ethernet.
The problem is that I'm getting drastic slowdown of throughput over time of usage. First I'm getting stable 22 Mbit/s, then after some time bandwidth fluctuate down and up and then finally it gets down to crappy speed. I can't even see it in the jpetf utility (GUI version of iperf) - sometimes it make peak to full bandwidth for a few seconds then it fall back to like 100 kBit/s. I don't see anything suspicious in Wireshark log or in LWIP stats display either. It just runs slow.
As I said...this code works fine on VC707 board so I suspect there is maybe something work with Axi EthernetLite/MII to RMII cores.
There are some critical warnings in implemented design:
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN2.RER_FF'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN2.TEN_FF'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[0].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[0].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[1].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[1].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[2].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[2].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[3].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[3].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
Is it possible source of the problem. How can I fix it?
Just saying I'm pure embedded C developer...I have made this design with help of your tutorials/reference stuff.
I would like to get some advice or get kicked to right direction in finding source of problem. Is possible to get some information about ethernet driver from LWIP? Is possible reset these IP cores from Microblaze?
Question
Dst
Greetings,
I'm developing TCP application based on the LWIP RAW and I'm stucked with a strange behaviour with similar hdl design and same application code on two different hw platforms - the trainer board Nexys 4 DDR and evaluation board Xilinx VC707
My problem is that everything works on VC707 board (for now).
My application code is a TCP server what sends continually data to connected client. I was testing this code thoroughly so it handles every possible situations (reset, abort flags, unplugged cable, connecting more clients...), dumping LWIP stats to check if there are some memory leaks and another stuff. I left this board to do its job for couple of hours/days without a problem. It just lives like I want.
The HDL design is simplified reference design for VC707 (Microblaze, DMA, AXI Ethernet...). The softprocessor is set for best performance (optional settings for instructions, cache and stuff).
I'm sharing VC707 with another colleague so sometimes I continue with the development on "slower" board Nexys 4 DDR. HDL design is the same like here https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start
So only difference is ethernet part - Axi EthernetLite and MII to RMII cores. VC707 has the gigabit ethernet.
The problem is that I'm getting drastic slowdown of throughput over time of usage. First I'm getting stable 22 Mbit/s, then after some time bandwidth fluctuate down and up and then finally it gets down to crappy speed. I can't even see it in the jpetf utility (GUI version of iperf) - sometimes it make peak to full bandwidth for a few seconds then it fall back to like 100 kBit/s. I don't see anything suspicious in Wireshark log or in LWIP stats display either. It just runs slow.
As I said...this code works fine on VC707 board so I suspect there is maybe something work with Axi EthernetLite/MII to RMII cores.
There are some critical warnings in implemented design:
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN2.RER_FF'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN2.TEN_FF'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[0].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[0].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[1].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[1].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[2].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[2].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[3].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
[Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[3].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
Is it possible source of the problem. How can I fix it?
Just saying I'm pure embedded C developer...I have made this design with help of your tutorials/reference stuff.
I would like to get some advice or get kicked to right direction in finding source of problem. Is possible to get some information about ethernet driver from LWIP? Is possible reset these IP cores from Microblaze?
Thanks and Regards
Daniel
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