Digital Discovery: Pulled-up DIO causes glitch when tri-stated

[dale_b_cooper]

I use Waveforms (digital pattern generator) of the Digital Discovery V1 (DigDisc). I setup one DIO (e.g. #27) to be a tri-state pin with 1.8V. I also attached a 1.8kOhm resistor to Vio (alternatively an externa voltage source). The issue occurs when a '1' is actively driven driven by the DigDisc and i then switch to 'Z' (tri-state). Then I see a short dip towards ground. This dip gets deeper the higher the DIO drive is set.  When using the minimum of 2mA the dip is about 600mV. 

Since there is an external pull-up the only explanation for this dip is that the DigDisc shortly drives the DIO low for an unknown reason instead of simply releasing the DIO. Now how to overcome this issue?

Any thought is appreciated.

 

Matt

[attila]

Hi @dale_b_cooper

There should be no glitch in such transition.
Could you attach a screenshot with your Pattern Generator setup ?

[dale_b_cooper]

Hi attila.

Thank you for your prompt reply. Please find attached my setup. Please note that I tried Vio supplied by DigDisc as well as by an external voltage source. Situation is the same in both cases. I also tried using different DIOs but always the same situation. All the DIOs seem to come from the same FPGA bank. Unfortunately the pins #0..#23, which are on a different bank, are input only.

Since I tried the High-Z mode weeks ago and did not see this issue I suspect a hardware issue with the DigDisc :(

Matt

[attila]

Hi @dale_b_cooper

I don't remember this issue, but newer software version works correctly.

 

[dale_b_cooper]

Hi @attila.

Thank you very much. You solved my issue. Apparently I installed an older software version when re-installing my laptop. This version caused the issue. With the latest software version the problem is gone. Now I just have to get used to the new way of setting the pattern clock speed :)

Thank you for your support.

Matt