SPI0 on Zybo 7000

[DMoore]

Hello all,

I am trying use the Zybo 7020 as a peripheral (slave) to communicate with an external master. I am pretty new to Vivado and Vitis and am having quite a few problems. I am trying to use the "xspips" library in Vitis that Xilinx provides and haven't been able to get it working as I don't know where/how to interact with the pins on the Zybo board. I have tried to connect the SPI0 signals in the block diagram to one of the pmod ports on the board, but it doesn't seem to be possible to do so.

If someone could give a tutorial on connecting signals to MIO header pins / ports on the board that would be wonderful, I am really struggling to find a lot of resources for later releases of Vivado.

Thanks.

[JColvin]

Hi @DMoore,

I don't know which version of Vivado you are using or if you are wanting to se the EMIO vs the MIO pins that are connected to Pmod port JF, but I'll see if I can help answer either option.

In terms of the SPI0 on EMIO, you'll be able to set this within the Zynq 7 IP block in the MIO Configuration tab. Once you have set it to EMIO, the SPI_0 will then show up as its own interface on the Zynq block, as indicated in this specific post here:

If you wanted to then connect those pins you can mark the interface as external and then assign those pins (such as SPI0_SCLK_I) to whatever Pmod pin.

In terms of using Pmod JF (which is connected to GPIO by default, but that might be a benefit since I don't think Xilinx/AMD has ready built SPI slave setups, so bit-banging through GPIO might be easier in this case), because the pins are directly connected to the PS (rather than the PL) you won't see the pins on the block design but will be able to the XGpioPS drivers. This is described a bit more in this thread here:

Let me know if you have any questions.

Thanks,
JColvin