set user assigned specific port value

[Dniel.Schmid]

As a newbi when trying to generate a bitstream file i get the following message, where/how to solve?

NSTD #1 62 out of 62 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify  all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard  value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the   implementation run. Problem ports: GPIO[10], GPIO[11], GPIO[12], GPIO[13], GPIO[14], GPIO[15], GPIO[1], GPIO[2], GPIO[3], GPIO[4], GPIO[5], GPIO[6], GPIO[7], GPIO[8], GPIO[9]  (the first 15 of 62 listed). 

[Viktor Nikolov]

My first guess is that you don't have a constraints file (.xdc) defined in your HW design. Or you do, but you do not set IOSTANDARD attribute for the ports.

[Dniel.Schmid]

Dear Viktor, thanks for your answer. Indeed, i have no constraints file, only verified verilog files. How/where to set  IOSTANDARD attribute for the ports? How/where to set constraints?

[Viktor Nikolov]

Good start for beginners is this guide provided by Digilent. It explains, among other things, how to create constraints file and how to get constraints file template for the board you are using.

[Dniel.Schmid]

Dear Viktor

Thanks for the help. Have read the guide and tried to load the constraints file from vivado-boards-master.zip. But there was no .xdc in the nesxis-A7-100T directory (see attachement), only board.xml, mig.prj, part0_pins.xml, preset.xml?

Best regards

Daniel

[Viktor Nikolov]

I'm not sure I understand.

When I download the https://github.com/Digilent/digilent-xdc/archive/master.zip and uncompressed it to a folder on my computer, it does contain the file Nexys-A7-100T-Master.xdc .

You need to add this single file as constraints file to you HW project in Vitis.

Edited April 8 by Viktor Nikolov

[Dniel.Schmid]

Dear Viktor,

thank you so much, it generates the bitstream now and works fine,

wish you all the best,

kind regards, Daniel.

Edited April 9 by Dniel.Schmid