Dniel.Schmid

Dear Viktor, thank you so much, it generates the bitstream now and works fine, wish you all the best, kind regards, Daniel.

Dear Viktor Thanks for the help. Have read the guide and tried to load the constraints file from vivado-boards-master.zip. But there was no .xdc in the nesxis-A7-100T directory (see attachement), only board.xml, mig.prj, part0_pins.xml, preset.xml? Best regards Daniel

Dear Arthur Thanks for your reply. What is your intention then with the EvalBoards? How would you do for a customisation? Kind regards Daniel

After having set up and used the NEXIS-A7-100T EvalBoard, i think about develop it into a more user specific board (add some devices and remove some). Now the question is, where to get the board design files (CAD files a/o GERBER files)? Does anybody have experience with such?

Dear Viktor, thanks for your answer. Indeed, i have no constraints file, only verified verilog files. How/where to set IOSTANDARD attribute for the ports? How/where to set constraints?

As a newbi when trying to generate a bitstream file i get the following message, where/how to solve? NSTD #1 62 out of 62 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPIO[10], GPIO[11], GPIO[12], GPIO[13], GPIO[14], GPIO[15], GPIO[1], GPIO[2], GPIO[3], GPIO[4], GPIO[5], GPIO[6], GPIO[7], GPIO[8], GPIO[9] (the first 15 of 62 listed).

Hi all, have the eval board Digilent NEXIS A7-100T with a flash ram S25FL128SAG. How to know to which variant in Vivado "Tools" ¦ "Generate configuration memory file" ¦ "Select Configuration Memory Part" this corresponds? any help is most appreciated, thanks. /daniel

Hi JColvin Thanks a lot for your helpful answer. I'm using Vivado 2023.2 AMD Vivado ML Edition. Found and corrected the error. best regards daniel

Dear Ladies and Gentleman Recently i bought the Digilent NEXIS-A7-100 EvalBoard and would like to use it for a potential product. So i have installed the Vivado Tool and tried to program the Xilinx FPGA on the Digilent NEXIS-A7-100 EvalBoard. But when running in Vivado first step "run synthesis" in the keyboard demo there is an error message about a D:\... drive (see attachement); but i have only a C:\... drive? how to overcome this hurdle? thanks a lot for advise, with best regards Daniel Schmid, Switzerland