Woody Arnold Posted October 3, 2016 Share Posted October 3, 2016 Good Afternoon ! My colleague and I are having issues interfacing the PmodGRYO (SPI Mode)to the Basys3 board using Verilog. Do any of you experienced users have any Verilog interface coding you can share? I tried finding this on the Digilent web site but to no avail. Thanks, Woody Link to comment Share on other sites More sharing options...
jpeyron Posted October 3, 2016 Share Posted October 3, 2016 Hi Woody, Here is a link to the PmodGYRO reference page where there is a Nexys 3 Verilog Example in ISE 14.2. You will need to make a few changes for it work in vivado. Mainly a different constraint file i.e. the xdc for the basys 3 instead of the Nexys 3 ucf file. You should be use this example for your project with just some copy and paste of the verilog files. Hope this helps! cheers, Jon Link to comment Share on other sites More sharing options...
Woody Arnold Posted October 4, 2016 Author Share Posted October 4, 2016 Thank- you Jon ! Much appreciated ! Woody Link to comment Share on other sites More sharing options...
Woody Arnold Posted October 21, 2016 Author Share Posted October 21, 2016 Jon provided me a link to the Nexis3 Verilog coding for the PmodGryo module. Does anyone know if there is a test bench to exercise this ? Just curious ! Any help will be greatly appreciated. Thank-you ! Woody Link to comment Share on other sites More sharing options...
jpeyron Posted October 24, 2016 Share Posted October 24, 2016 Hi Woody, Here is a pdf about "Writing Efficient Testbenches" and here's a pdf of the "Vivado Design Suite Tutorial Logic Simulation". Hope this helps! thank you, Jon Link to comment Share on other sites More sharing options...
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