DVI2RGB IP questions

[Ppspendse]

Hi, I am trying to simulate the DVI2RGB IP. I am new to this DVI signalling parameters, can anyone provide me any example projects to simulate and understand the data flow and clk parameters. Thanks in advance

[artvvb]

Hi @Ppspendse

Digilent doesn't provide example simulation sources for this core. If you haven't, please refer to the user guide: https://github.com/Digilent/vivado-library/blob/master/ip/dvi2rgb/docs/dvi2rgb.pdf. Sections on clock recovery and designing with the core should be helpful. Several other documents it references, including DDWG's DVI spec, may also help.

Thanks,

Arthur

[Ppspendse]

On 2/20/2024 at 6:27 PM, artvvb said:

Hi @Ppspendse

Digilent doesn't provide example simulation sources for this core. If you haven't, please refer to the user guide: https://github.com/Digilent/vivado-library/blob/master/ip/dvi2rgb/docs/dvi2rgb.pdf. Sections on clock recovery and designing with the core should be helpful. Several other documents it references, including DDWG's DVI spec, may also help.

Thanks,

Arthur

Hi Arthur,

Thanks for your inputs. so you mean to say that the block doesnt have provision to simulate and test ?. my example project is checking the two IPs rgb to dvi and dvi to rgb. in doing so i have come up with a technique. I am generating TMDS output from the rgb to dvi ip. but when I connect my tmds clk and data of rgb to dvi ip to dvi to rgb ip clks get generated but i can not see the rgb data getting generated back.any help would be appriciated.

Thank you,

Purushottam

Edited February 27 by Ppspendse

[artvvb]

Could you share the rgb_gen source and IP configuration settings?

Looking at the block design, please check your reset polarity. The "locked" outputs from the clocking wizard IPs are active high - when high, they indicate that the clocks are working. It looks like rgb2dvi and your rgb_gen module are working, but the data path through dvi2rgb may not be. Both dvi2rgb and rgb2dvi have active high resets by default, which are used in your design.

What Digilent provides to test and debug the core is described in the "Debugging" section of the dvi2rgb IP core user guide, there are some internal logic analyzers that can be optionally instantiated and used to check signals while a board is programmed, but no simulation sources are provided (though you can still create testbenches yourself, as you are doing). Based on its datasheet, rgb2dvi doesn't have similar debugging logic.

[Ppspendse]

11 hours ago, artvvb said:

Could you share the rgb_gen source and IP configuration settings?

Looking at the block design, please check your reset polarity. The "locked" outputs from the clocking wizard IPs are active high - when high, they indicate that the clocks are working. It looks like rgb2dvi and your rgb_gen module are working, but the data path through dvi2rgb may not be. Both dvi2rgb and rgb2dvi have active high resets by default, which are used in your design.

What Digilent provides to test and debug the core is described in the "Debugging" section of the dvi2rgb IP core user guide, there are some internal logic analyzers that can be optionally instantiated and used to check signals while a board is programmed, but no simulation sources are provided (though you can still create testbenches yourself, as you are doing). Based on its datasheet, rgb2dvi doesn't have similar debugging logic.

Yes the rgb gen and rgb to dvi are working and the datapath through dvi to rgb is not working.. I will share the updated design now.

 

 

rgb_gen.vhd

[Ppspendse]

2 minutes ago, Ppspendse said:

Yes the rgb gen and rgb to dvi are working and the datapath through dvi to rgb is not working.. I will share the updated design now.

 

 

rgb_gen.vhd 3.29 kB · 0 downloads

is it possible for you to give a vhdl source code that would generate tmds data and clock, so that I feed it to my dvi to rgb block and check for data flow?