Multichannel Audio with Xilinx I2S Rx / Tx & Audio Formatter

[vz49]

Hi, I have been using the Xilinx audio formatter, i2stx and i2srx ips for 2 channel (stereo) audio application with success.

 

My project requires multichannel audio. As the IP suggested, I should be able to transmit 8 channels (4x stereo pair) from the audio formatter to i2stx. So far, I can only configure the ip and software driver up to 6 channels output (3x stereo) with success. No matter how many times i tried and debugged, I cannot output 8 channels (4x stereo).

 

I have attached an ILA logic analyzer to monitor the axis stream data line (Audio Formatter) and the output of the I2STx. The data is corrupted once my output channel counts increase from 6 to 8. The I2STx tready is jittering, looks like the the I2STx is "suffocating" or "choked" with incoming data.

 

I further investigate and found out that the Axi Stream (Tready) line is working properly at the very beginning (Audio Formatter DMA Start), then it gets jittery very quickly.

 

 

The Config on the Audio Formatter IP are:

Read

8 Channels

Interleaved

PCM to AES

32 Bit address width

 

The Config on the I2STx IP are:

8 Channels

24Bit

32BitLRCLK (checked)

FIFO=1024

 

Am I missing anything? I have been using the 6 channel configuration between these two ips with no problem for a long time. Does anyone have any successful use of AudioFormatter and I2STx in multichannel (8 Channel) application? Would like to have some guidance and advice about setting them up properly.

 

Thanks.

 

Vincent

[zygot]

Have you read the IP documentation?

[vz49]

@zygot I have managed to setup a 6 channel audio output with success previously. Again, once I jump from 6 to 8. Everything simply not working well.

From vivado (ip configuration) to vitis (drivers and code), I have tried my very best to setup every parameter carefully. Still I have no luck. So I just wonder if anyone has success experience with 8 channel audio outputs before.

If you did, I would like to hear from you.

Cheers.

Vincent

[zygot]

Well out of curiosity I tried to find the IP documentation that you are using. Without actually signing into my AMD account I was totally unsuccessful. Finding documentation for AMD/Xilinx products has definitely gotten harder recently, especially on a Linux host, unless you sign into your account.

Using FPGA vendor IP is not as simple as configuring it in the IP wizard. That's why you need to read the documentation. While IP may support a wide range of configuration settings that doesn't mean that there aren't restrictions among all of the possibilities. Just because you had success with 6 channels doesn't mean that changing the number of channels from 6 to 8 automatically works without some modification. I've never used this IP so I have not experience with it.

The first thing for you to do is read all of the synthesis and implementation warnings to see if there are clues to what's changed in your modified design Usually, Xilinx IP comes with a simulation testbench. Simulation is the key to all FPGA design flows. AXI based simulation is generally messier and more complicated than regular HDL simulation, especially for a ZYNQ target.

If you can't figure out how to debug your design then this is a problem. FPGA vendor IP usually is very hard to unwind so that you can understand how it works. It you can't do an effective simulation of your design, then you need to be clever about figuring other ways of debugging what the tools are giving you. . Edited February 16 by zygot

[vz49]

Ok. A bit of update from my debugging session. I have attached an ILA analyzer to the Audio Formatter MM2S axis output.

 

The signal <<m_axis_mm2s_tid[7:0]>> is supposed to tell the audio channel number id for each data packet sent out. 

Let say I am running the 6 channel configuration the tid would be 0 - 5 (Channel 1 - Channel 6). This is correct tid signal from a good working 6 channel setup.

When I am running the 8 channel configuration, the tid value, from ILA, goes from 0-9 (Channel 1 - Channel 10), instead of 0-7.

That explains why, as i mentioned in my first post, the reciever on the other end is "choked" and "suffocated", since there is more data input than expected.

Now, I have to trace what makes the Audio Formatter IP outputting 10 channels of data when it was told to only output 8 Channel.

I have tired to aligned my audio buffer to 32bit , 64bit and 256bit. Still does not help with the fact that it is outputting more than asked.

Any thoughts?

Vincent

Edited February 17 by vz49

[zygot]

I suppose that anything's possible; but it seems highly improbable that Vivado IP would create an instance where there are more channels than it is capable of creating.

Without reading the IP documentation or doing simulation you have a challenging task in figuring out what's going wrong. Trying to debug something that you don't understand, and don't even have access to IP documentation, which can be sketchy at best, is tough.

My guess is that you aren't seeing any, much less 10 channels with complete data frames. As the amount of data increases per frame it's reasonable to suspect timing and clocking as a source of your problems.

Have you worked you way through the IP source code?

My suggestion is to create your own IP using the HDL flow and abandon the VIvado IP if you can't read the documentation or do a proper simulation.

[vz49]

ok. After some investigation with register values, I realized that, the register value showing the number of active channels  for Audio Formatter is 10, this is why it is trying to output 10 channels. I config the audio formatter ip, using Xilinx IP drivers and set the number to 8. However, via register checking, the value turns out to 10. I fix it by "manually" modify the register value using pointer. There might be some bug with the original Xilinx Audio Formatter drivers.

The IP is now running at expected with no data corruption, as long as the register is configured correctly.