vz49

ok. After some investigation with register values, I realized that, the register value showing the number of active channels for Audio Formatter is 10, this is why it is trying to output 10 channels. I config the audio formatter ip, using Xilinx IP drivers and set the number to 8. However, via register checking, the value turns out to 10. I fix it by "manually" modify the register value using pointer. There might be some bug with the original Xilinx Audio Formatter drivers. The IP is now running at expected with no data corruption, as long as the register is configured correctly.

Ok. A bit of update from my debugging session. I have attached an ILA analyzer to the Audio Formatter MM2S axis output. The signal <<m_axis_mm2s_tid[7:0]>> is supposed to tell the audio channel number id for each data packet sent out. Let say I am running the 6 channel configuration the tid would be 0 - 5 (Channel 1 - Channel 6). This is correct tid signal from a good working 6 channel setup. When I am running the 8 channel configuration, the tid value, from ILA, goes from 0-9 (Channel 1 - Channel 10), instead of 0-7. That explains why, as i mentioned in my first post, the reciever on the other end is "choked" and "suffocated", since there is more data input than expected. Now, I have to trace what makes the Audio Formatter IP outputting 10 channels of data when it was told to only output 8 Channel. I have tired to aligned my audio buffer to 32bit , 64bit and 256bit. Still does not help with the fact that it is outputting more than asked. Any thoughts? Vincent

@zygot I have managed to setup a 6 channel audio output with success previously. Again, once I jump from 6 to 8. Everything simply not working well. From vivado (ip configuration) to vitis (drivers and code), I have tried my very best to setup every parameter carefully. Still I have no luck. So I just wonder if anyone has success experience with 8 channel audio outputs before. If you did, I would like to hear from you. Cheers. Vincent

Hi, I have been using the Xilinx audio formatter, i2stx and i2srx ips for 2 channel (stereo) audio application with success. My project requires multichannel audio. As the IP suggested, I should be able to transmit 8 channels (4x stereo pair) from the audio formatter to i2stx. So far, I can only configure the ip and software driver up to 6 channels output (3x stereo) with success. No matter how many times i tried and debugged, I cannot output 8 channels (4x stereo). I have attached an ILA logic analyzer to monitor the axis stream data line (Audio Formatter) and the output of the I2STx. The data is corrupted once my output channel counts increase from 6 to 8. The I2STx tready is jittering, looks like the the I2STx is "suffocating" or "choked" with incoming data. I further investigate and found out that the Axi Stream (Tready) line is working properly at the very beginning (Audio Formatter DMA Start), then it gets jittery very quickly. The Config on the Audio Formatter IP are: Read 8 Channels Interleaved PCM to AES 32 Bit address width The Config on the I2STx IP are: 8 Channels 24Bit 32BitLRCLK (checked) FIFO=1024 Am I missing anything? I have been using the 6 channel configuration between these two ips with no problem for a long time. Does anyone have any successful use of AudioFormatter and I2STx in multichannel (8 Channel) application? Would like to have some guidance and advice about setting them up properly. Thanks. Vincent

@elodgI am happy to report that using the "custom genesys zu5ev repo" inside vitis has been great and smooth. The DDR4 HyperX is initialized and run successfully using the 5ev board preset inside Vivado. I typed "set_property CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN 1 [get_bd_cells /zynq_ultra_ps_e_0]" in the tcl console to make sure the te dynamic ddr config feature is on. Thanks for the help. Appreicate it! Best, Vincent

@elodg Hi, thanks for the feedback. I have just tested the Hello World Example on my 5EV, it works beautifully. You mentioned that the dynamic DDR initialization only works on xilinx "approved" developement board, including the the Genesys. Does it mean that all custom zynq mpsoc board cannot access this feature? If that is the case, it is better to setup the DDR4 config directly inside Vivado. Forgive me I am a novice, I simply has no clue how to setup the HyperX Ram supplied on the 5EV. It seems the datasheet is not providing full info of how the ram should be setup. It would be great if digilent can provide a solid setting of the HyperX Ram inside Vivado DDR setup, therefore users does not have to fiddle with the FSBL DDR Initialization hassle unless they choose to upgrade to different model. Let me know if I am optimalistic or wrong. Once again, thanks for the headup. Cheers.

Hi there, I have a difficult time setting up the HyperX HX424S14IB/4 DDR4 ram on my Genesys zu5EV board. What I have tried: 1. using the 5EV board presets without any changes. 2. Enabling Dynamic DDR Configuration in Vivado 3. Try to setup the values inside the DDR controller windows inside the MPSOC IP. Unfortunately, the amount of info i can get from the manufacture datasheet is very limited. Link: https://www.kingston.com/dataSheets/HX424S14IB_4.pdf So far I have no success running a simply "hello world" baremetal application on ddr. Obivously, I tweak the Linker Script to run my code on OCM only. Everything is working perfectly without ddr. I am pretty sure that, the DDR controller is not setup/ Intitalized correctly to communicate with the HyperX HX424S14IB/4, therefore loading the code on to ddr is impossible and leads to error: "Error while launching program: Memory write error at 0x0. Cortex-A53 #0: EDITR not ready" I did some reading on this forum that it is something to do with the FSBL, and this issue is not 100% solved even to this day. Let me know if I am wrong. I wish someone can jump in and give me some guidence. I am using Vivado 2022.1 and Vitis 2022.1 Thanks Vincent